Active filter calibration method and apparatus
Granted: November 30, 2010
Patent Number:
7843257
An example bandpass filter calibration system includes a MUX, first and second signal sources coupled to inputs of the MUX, a bandpass filter coupled to an output of the MUX, a rectification circuit including a plurality of rectifiers having a corresponding plurality of rectifier outputs coupled to an output of the bandpass filter, a summer having a plurality of inputs coupled to the plurality of rectifier outputs, a low pass filter coupled to an output of the summer, an ADC coupled to…
Magnetic stripe reader having digital peak detector
Granted: November 23, 2010
Patent Number:
7837110
A point of sale terminal includes a microcontroller integrated circuit. In one aspect, a regulator within the IC receives power from a supply voltage terminal and/or a battery terminal. If the regulator does not receive adequate power from either terminal, then energy stored on-chip in a capacitor is used to erase secure memory. In another aspect, pulses of current are made to pulse through conductors of a conductive mesh. A tamper condition is detected if an improper voltage is detected…
Method and apparatus for cancellation of magnetizing inductance current in a transformer circuit
Granted: November 23, 2010
Patent Number:
7839938
A feedback method and apparatus for cancellation of magnetizing inductance current are presented. A voltage driver applies a voltage signal to a primary of a transformer. Feedback apparatus detect changes in the voltage driver output current that are attributable to magnetizing inductance current. Changes in output current are used to obtain a current error, which is integrated to control a current ramp generator. The output of the current ramp generator is applied to the transformer…
Thermally optimized architecture for switching regulators
Granted: November 16, 2010
Patent Number:
7834598
In a preferred embodiment for use in step-down (buck) DC-DC converters that may operate, at least part of the time, at high duty cycles (>50%), the power dissipation in the high side switch is effectively monitored and the switching frequency of the converter is lowered as needed to keep the sum of the conduction losses and switching losses in the high side switch substantially constant. In another embodiment, the ideal switching frequency is approximated. In still another embodiment…
EEPROM memory cell with first-dopant-type control gate transister, and second-dopant type program/erase and access transistors formed in common well
Granted: November 16, 2010
Patent Number:
7835184
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
Method of programming a selected memory cell
Granted: November 16, 2010
Patent Number:
7835186
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
System and method for compensating pulse generator for process and temperature variations
Granted: October 19, 2010
Patent Number:
7816967
An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ?VGS current source to generate a second current through a resistor to produce a second voltage V2; a comparator to generate the pulse in response to the first and second voltages; and a circuit to enable the charging and…
Input-voltage-rate-of-change-dependent current-limit set point for hot-swap controllers
Granted: October 12, 2010
Patent Number:
7813094
Certain exemplary embodiments disclosed herein include an adaptive current limiter comprising a variable reference voltage generator which is coupled to a power source via two input nodes and which develops a voltage step with exponential decay in response to, for example, a transient over-voltage condition, with the output of the variable reference voltage generator supplying a reference voltage to a comparator which compares the reference voltage to a voltage derived from a sensing…
Methods and apparatus for adding an autonomous controller to an existing architecture
Granted: September 21, 2010
Patent Number:
7802043
Methods and apparatus for adding an autonomous controller to an existing architecture such as by way of example, portable devices such as cell phones, MP3 players, and digital cameras. A circuit interposed between the memory card and the system controller of the device is controllable to couple the memory card to the system controller, or to couple the memory card to a high speed I/O controller on the circuit. When the memory card is coupled to the high speed I/O controller on the…
Method of erasing a block of memory cells
Granted: September 7, 2010
Patent Number:
7791955
A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is…
Adaptive current limiting for any power source with output equivalent series resistance
Granted: August 24, 2010
Patent Number:
7782018
Adaptive current limiting for any power source to limit power drain of one load on the power source to maintain a minimum power source voltage for proper operation of other loads on the power source. For battery applications, such as for flash systems, the invention allows the maximum output current of a boost converter to be utilized without having to calculate the system equivalent series resistance first. The invention also adjusts the current load up or down during a high load event…
System and method for transform coding randomization
Granted: August 17, 2010
Patent Number:
7778476
A method and system are provided where image data is encoded in the spatial domain, and transformed in a two dimensional transform process to thereby recover a frequency domain representation of the image data. The frequency domain representation is then quantized to obtain an integer representation. The integer representation is ordered by frequency. Then, the hi-frequency coefficients are recreated and intelligently randomized at selective frequencies. This provides high quality…
Bias circuit with non-linear temperature characteristics
Granted: August 3, 2010
Patent Number:
7768342
In an embodiment, a current source having a piece-wise linear relationship between current and temperature is provided. The current source includes a first current source to provide current based on a first current-temperature relationship. The current source further includes a second current source coupled in parallel to the first current source. The second current source is to provide current based on a second current-temperature relationship. The current source further includes first…
Bulk acoustic resonators with multi-layer electrodes
Granted: August 3, 2010
Patent Number:
7768364
Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W.
Methods and apparatus for simultaneous automatic gain, phase and DC offset correction in communication receivers
Granted: August 3, 2010
Patent Number:
7769116
Described herein is a method of automatic gain control and simultaneous digital correction of three types of variations in I/Q receivers: gain imbalance, phase imbalance, and DC offset. Three adaptation loops can operate simultaneously and use the output of an analog to digital converter (ADC) as their input, with the output driving digitally controllable analog components. With appropriate knowledge of signal statistics, the algorithm automatically optimally fills the ADC's full input…
Hardware multithreading systems with state registers having thread profiling data
Granted: July 27, 2010
Patent Number:
7765547
According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls.…
Method and apparatus for providing an adaptive current limiter
Granted: June 29, 2010
Patent Number:
7746613
An adaptive current limiter is coupled to a power source and which comprises a variable reference voltage generator which provides a variable reference voltage which is inversely proportional to the input voltage from the power source, which in certain embodiments is representative of the maximum allowable current level that may flow through a connected load at the present voltage provided by the power source given a fixed power limit. The current flow to the load is interrupted when the…
BAW resonator bi-layer top electrode with zero etch undercut
Granted: June 15, 2010
Patent Number:
7737612
A piezoelectric resonator includes a multi-layer top electrode configured such that a top most layer protects the underlying layers from subsequent etching, thereby preventing etch undercut of the top-most layer. In one embodiment, the multi-layer top electrode is configured as a bi-layer, so that the upper layer of the bi-layer stack protects all sides of the underlying layer from subsequent etch process steps. In an alternative embodiment, at least the perimeter of a multi-layer top…
Self configuring output stages of precision amplifiers
Granted: June 15, 2010
Patent Number:
7737784
Self configuring output stages of precision amplifiers that remain linear when operating into a load that may have a ground reference below the amplifier ground reference, that maintain full amplifier gain while approaching zero output, and that can provide a zero output even when operating into a load that may have a ground reference below the amplifier ground reference, that has a self configuring output stage operable with either a mid-rail or ground reference below amplifier ground,…
Method and/or architecture for controlling encoding parameters using integrated information from camera ISP
Granted: June 8, 2010
Patent Number:
7733380
A camera including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing and control one or more functions of the camera using image signal processing related information and encoding related information. The second circuit may be configured to encode image data using the image signal processing related information and camera settings information. The first circuit may be further configured to pass the image signal processing related…
