Method and System to Provide a Polysilicon Capacitor with Improved Oxide Integrity
Granted: May 21, 2009
Application Number:
20090130813
A system and method in accordance with the present invention allows for an improved oxide integrity of a polysilicon capacitor compared to capacitors manufactured using conventional semiconductor processing techniques. This is accomplished by moving the capacitor implant step to a time after the deposition of the polysilicon. As an additional benefit, a separate capacitor oxide growth does not need to be performed.
SYSTEM AND METHOD FOR MATCHING SILICON OXIDE THICKNESS BETWEEN SIMILAR PROCESS TOOLS
Granted: May 14, 2009
Application Number:
20090125140
The present invention is one or more implementations is a method of fabricating a semiconductor for improved oxide thickness control, defining a process tool, determining and evaluating performance variables, determining a performance impact factor and thereafter modifying control of the process tool in the fabrication process to operate in direct relation to the determined results of the present invention. The present invention sets forth definitive advantages in reducing engineering…
Fast Settling Radio Receiver Automatic Gain Control System
Granted: May 7, 2009
Application Number:
20090117868
A fast settling AGC system includes a “fast settle” comparator that facilitates fast settling of strong radio receiver output signals from a maximum to an intermediate voltage level at the start of each transmission burst, and a “normal” AGC comparator that further settles the output signal from the intermediate voltage level to a desired target output voltage level at a slower “normal” rate. The gain control signal components generated by both the “fast settle”…
Method for forming Zener Zap Diodes and Ohmic Contacts in the Same Integrated Circuit
Granted: April 9, 2009
Application Number:
20090093116
A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact…
Light Emitting Diode Driver Circuit With Shunt Switch
Granted: April 2, 2009
Application Number:
20090085490
A LED driver circuit avoids undesirable light generated by a LED due to leakage current by shunting the output terminal to the feedback terminal during periods when it is desired that the LED remain turned off. The shunting operation is achieved by providing a switch (e.g., a FET) that is connected between the output and feedback terminals of the LED, and is controlled by the user supplied reference signal. During active operation (i.e., when the user supplied reference signal is…
DETECTION OF PRESENCE OR ABSENCE OF AC MAINTAIN POWER SIGNATURE IN POWER-OVER-ETHERNET SYSTEM
Granted: April 2, 2009
Application Number:
20090085586
An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense…
Power Distribution Current Limiting Switch Including A Current Limit Blanking Period Providing A Burst of Current
Granted: April 2, 2009
Application Number:
20090085643
A method for operating a current limit power switch for supplying power to a load include activating the power switch to start supplying power to the load; limiting the current drawn by the power switch to a first current limit for a first, fixed duration; after the first, fixed duration, limiting the current drawn by the power switch to a second current limit for a second duration where the second current limit is less than the first current limit; and after the second duration,…
Low Current Method For Detecting Presence of Ethernet Signals
Granted: March 5, 2009
Application Number:
20090059948
A signal detection circuit for an Ethernet physical layer transceiver (PHY) device includes a first capacitor AC coupling a signal on the first receive terminal of the Ethernet PHY device to a first node; a second capacitor AC coupling a signal on the second receive terminal to a second node; re-biasing resistors for re-biasing the AC-coupled signals on the first and second nodes; first and second gain stages for amplifying the AC coupled signals; and a peak detect circuit. The peak…
Power Budget Management In Power Over Ethernet Systems
Granted: February 26, 2009
Application Number:
20090055672
A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node…
LED Controller IC Using Only One Pin to Dim and Set a Maximum LED Current
Granted: February 5, 2009
Application Number:
20090033243
An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal…
N-channel MOS Transistor Fabricated Using A Reduced Cost CMOS Process
Granted: February 5, 2009
Application Number:
20090032850
An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped…
Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics
Granted: January 29, 2009
Application Number:
20090026578
A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the…
INTEGRATED CIRCUIT SYSTEM FOR LINE REGULATION OF AN AMPLIFIER
Granted: January 22, 2009
Application Number:
20090021306
An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier.
SYSTEM AND METHOD FOR PHASE-LOCKED LOOP (PLL) FOR HIGH-SPEED MEMORY INTERFACE (HSMI)
Granted: January 22, 2009
Application Number:
20090021310
A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually…
Line Protection Load Switch For Portable Device
Granted: January 15, 2009
Application Number:
20090015977
A portable device includes a voltage regulator for generating a regulated voltage that is supplied to a processor and to a load by way of a line protection switch, which controls a load current supplied to the load, e.g., in response to a signal supplied by the processor. The line protection switch includes a gate control circuit with a comparator that detects a short circuit in the load by comparing the regulated voltage against a reference voltage. When a short circuit causes the…
Laser Driver Automatic Power Control Circuit Using Non-Linear Impedance Circuit
Granted: January 15, 2009
Application Number:
20090016392
A laser driver circuit includes a laser APC circuit receiving a monitor current indicative of the average optical output power of a laser diode and providing a bias adjust signal for adjusting a bias current for the laser diode. The laser APC circuit includes a first non-linear impedance circuit receiving the monitor current and generating a first voltage using a first non-linear current-to-voltage transfer function, a second non-linear impedance circuit receiving a reference current and…
PON Burst Mode Receiver with Fast Decision Threshold Setting
Granted: December 18, 2008
Application Number:
20080310861
A receiver converts an analog signal, derived from light pulses in a GPON fiber optic system, to clean digital electrical signals. A photodetector and transimpedance amplifier (TIA) convert the light pulses to analog electrical signals. A reset signal generated by a media access controller (MAC) in the GPON system signifies the start of a new burst of data. The receiver has a switchable low pass filter that establishes the threshold voltage for determining whether the analog signal is a…
Power FET With Low On-Resistance Using Merged Metal Layers
Granted: December 11, 2008
Application Number:
20080303097
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is…
INTEGRATED CIRCUIT SYSTEM FOR ANALOG SWITCHING
Granted: December 4, 2008
Application Number:
20080297227
An integrated circuit system comprising: forming an analog switch including: providing a current source for driving the analog switch, coupling a first source follower to the current source for forming a first input to the analog switch, coupling a second source follower to the current source for forming a second input to the analog switch, and coupling a switch to the first source follower and the second source follower for selecting the first input, the second input, or a combination…
INTEGRATED CIRCUIT SYSTEM FOR CONTROLLING AMPLIFIER GAIN
Granted: December 4, 2008
Application Number:
20080297250
An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor.
