Self-starting reference circuit
Granted: November 8, 2005
Patent Number:
6963191
A reference circuit provides a reference electrical characteristic such as a current or voltage using a low-threshold field effect transistor (FET) for improved start-up operation. The use of a low-threshold FET eliminates a stable operating point from occurring at zero current allowing the elimination of additional startup circuitry thereby providing power and space savings, particularly in analog CMOS circuitry. Additionally, the use of a low-threshold FET allows a lower voltage…
Filter for digitally processing an analog input signal with analog feedback
Granted: October 11, 2005
Patent Number:
6954160
A filter is described for digitally processing an analog input signal with analog feedback. In one example, the filter uses a topology similar to a second order universal filter block and includes a signal combiner for producing an analog output signal based upon an analog input signal and one or more analog feedback signals. An analog to digital converter processes the analog output signal into a digital data stream which is digitally processed to produce one or more digital output…
Auxiliary output driver
Granted: October 4, 2005
Patent Number:
6952119
A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the…
Zero-cost non-volatile memory cell with write and erase features
Granted: September 27, 2005
Patent Number:
6949784
A memory device includes a coupling capacitor and a field-effect transistor. The coupling capacitor is formed from (1) a first dopant region in a second dopant region on a substrate, (2) a gate dielectric atop the first dopant region, and (3) a first gate conductor atop the gate dielectric. The coupling capacitor has the first gate conductor coupled to a second gate conductor of the field-effect transistor. A voltage can be applied to the second dopant region to isolate the coupling…
High frequency power amplifier
Granted: September 6, 2005
Patent Number:
6940353
A CMOS amplifier includes a CMOS inverter and a bias circuit coupled in a feedback loop between the output and input of the inverter. The bias circuit provides linear biasing so that the inverter can apply a desired gain to a high frequency input signal. The bias circuit can include an operational amplifier (op-amp) providing positive feedback control between the output and input of the inverter. By providing a reference voltage to the other input of the op-amp, the input of the inverter…
High frequency differential power amplifier
Granted: August 30, 2005
Patent Number:
6937071
A differential CMOS amplifier includes two CMOS inverters and biasing circuitry providing feedback loops across the output and input of each inverter. The biasing circuitry provides linear biasing so that the inverters can apply a desired gain to a pair of high frequency input signals (i.e., a differential input signal). The biasing circuitry can include operational amplifiers (op-amps) for providing positive feedback control between the output and input of the inverters. The inputs of…
Integrated Schottky transistor logic configuration
Granted: August 23, 2005
Patent Number:
6933751
A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to…
Measurement of optical power in optical fiber networks
Granted: August 23, 2005
Patent Number:
6934470
Systems and methods for the measurement of optical power in optical fiber are disclosed. The optical signal is converted to an electrical signal, which is then converted to a digital output code that indicates the relative strength of the optical signal in terms of logarithmic units.
Integrating chip scale packaging metallization into integrated circuit die structures
Granted: July 12, 2005
Patent Number:
6917105
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.
Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer
Granted: July 5, 2005
Patent Number:
6913981
Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a…
Method for fabricating a vertical bipolar junction transistor
Granted: June 14, 2005
Patent Number:
6905935
A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a…
Input terminal with combined logic threshold and reset function
Granted: June 7, 2005
Patent Number:
6903569
A circuit receives a first supply voltage on a first terminal where the first supply voltage is used to supply circuitry within the circuit. The circuit includes an input terminal receiving a first signal and an input circuit coupled to the input terminal. The first signal has a logical high value at a second voltage and a logical low value at a third voltage. The second voltage is used to establish a switching threshold of at least some of the input and output signals of the circuit.…
Integrating chip scale packaging metallization into integrated circuit die structures
Granted: May 31, 2005
Patent Number:
6900538
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary…
Method and apparatus for optimizing the accuracy of an electronic circuit
Granted: May 24, 2005
Patent Number:
6897662
The present invention provides an apparatus and method for improving the accuracy of circuits. The apparatus includes a replicate circuit and a trim determination circuit. The trim determination circuit includes a measurable circuit element and determines the state of the measurable element. The replicate circuit includes a replicate circuit element which has similar electrical characteristics as the measurable element, and is configured to aid in determining an adjustable test current.…
Minimization of overhead of non-volatile memory operation
Granted: May 24, 2005
Patent Number:
6898680
A method and structure are provided that reduce the overall time of the read-erase-modify-write cycle time of non-volatile memories. Specifically, the erase operation of the read-erase-write cycle is avoided in certain circumstances. In one embodiment, the erase operation is skipped where a predetermined pattern is found in at least a portion the block. In another embodiment, the erase operation is skipped where a status of the block indicates that the erase operation can be skipped.
Buried power bus utilized as a sinker for high current, high power semiconductor devices and a method for providing the same
Granted: May 17, 2005
Patent Number:
6894393
A method and system for providing a sinker on a semiconductor device is described. The method and system includes providing a substrate region and providing a buried layer and an epitaxial (EPI) layer over the substrate region. The method and system further includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the buried layer and the substrate region. The method and system finally includes oxidizing…
Method and system for high density integrated bipolar power transistor using buried power buss
Granted: May 10, 2005
Patent Number:
6891249
A method and system for providing a bipolar power transistor on a semiconductor device is disclosed. The method and system comprise providing a semiconductor substrate. The method and system includes providing an emitter base structure in the power device. The method and system further includes providing at least one oxidized slot through the emitter base structure and into the semiconductor substrate utilizing the highly inefficient portion of the emitter for this structure, thus wasted…
Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors
Granted: May 3, 2005
Patent Number:
6888710
An electrostatic discharge (ESD) protection circuit which includes an Insulated Gate Bipolar Transistor (IGBT), a collector clamp, and a resistor. The IGBT collector is coupled with a circuit pad, and the emitter is coupled to ground. The collector clamp is coupled with the pad and the IGBT gate, and the resistor is coupled with the IGBT emitter and gate. When the voltage at the pad is below the trigger voltage of collector clamp, the collector clamp remains in a blocking state, thus…
Buried power buss utilized as a ground strap for high current, high power semiconductor devices and a method for providing the same
Granted: April 19, 2005
Patent Number:
6882053
A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system comprises providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the…
Differential charge pump
Granted: April 5, 2005
Patent Number:
6876244
A differential charge pump includes common mode circuitry for supplying a common mode voltage to a charging capacitor in the charge pump. The gate voltage of a reference transistor in a biasing branch of the differential charge pump is adjusted until the drain voltage of the reference transistor is equal to the common mode voltage when a specified bias current is flowing through the biasing branch. The same gate voltage and bias current are provided to a first transistor in a first…
