Universal input apparatus
Granted: March 8, 2005
Patent Number:
6864707
Input structures and topologies are provided for coupling a differential input into a first stage of a circuit, topology, or device. An input pin is coupled to an impedance divider that translates an input voltage to accommodate low input voltage levels, while not saturating an input differential pair. A termination pair with a center tap pin is further coupled to the input pins. The center tap facilitates coupling different termination configurations to the input signal. The topologies…
Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
Granted: March 8, 2005
Patent Number:
6864537
An electrostatic discharge (ESD) protection circuit includes a transistor with a gate electrode isolated from the semiconductor substrate by a thick oxide, a collector clamp coupled with a pad and the gate electrode, and an emitter clamp coupled between the gate electrode and the emitter of the transistor. Until the pad voltage reaches a trigger voltage, the collector clamp does not conduct, thereby preventing the transistor from conducting. However, when the pad voltage reaches the…
Method for forming a SiGe heterojunction bipolar transistor having reduced base resistance
Granted: March 1, 2005
Patent Number:
6861323
A method for forming a heterojunction bipolar transistor includes forming an epitaxial layer, forming a first polysilicon layer, and forming a dielectric layer on the first polysilicon layer. The first polysilicon layer and the dielectric layer include an opening for exposing a portion of the top surface of the epitaxial layer. Then, a silicon germanium layer is selectively grown in the opening. The silicon germanium layer is grown on the exposed top surface of the epitaxial layer and on…
Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
Granted: March 1, 2005
Patent Number:
6861711
An electrostatic discharge (ESD) protection circuit that includes an transistor with a gate electrode isolated from the semiconductor substrate. The transistor can be an insulated gate bipolar transistor (IGBT) connected between an integrated circuit (IC) pad and ground. The IGBT includes a parasitic thyristor that latches when the voltage at the pad exceeds a threshold level and does not turn off until the charge at the pad is dissipated, thereby preventing electrostatic damage to the…
Selective high-side and low-side current sensing in switching power supplies
Granted: February 8, 2005
Patent Number:
6853174
A current mode switching regulator implementing a dual sense scheme includes a first current sensing circuit for sensing a current through a first switch and providing a first current sense signal, and a second current sensing circuit for sensing a current through a second switch and providing a second current sense signal. The switching regulator includes a control circuit for generating switch control signals for driving the first and second switches in response to one of the first and…
Triply implanted complementary bipolar transistors
Granted: January 4, 2005
Patent Number:
6838350
A method for fabricating a bipolar transistor includes forming a first region of a first conductivity type in a semiconductor structure to form a collector region and forming a second region of a second conductivity type in the first region to form a base region. A first mask is applied including an opening defining an emitter region of the bipolar transistor. The method further includes a triple implantation process using the first mask. Thus, a third region of the first conductivity…
LDMOS transistor with high voltage source and drain terminals
Granted: December 21, 2004
Patent Number:
6833586
An LDMOS transistor includes drift regions from the body to the drain and the source terminals and is capable of handling high voltages at both the source and drain terminals. In one embodiment, a transistor includes a body region formed in a first well, a conductive gate formed over a first dielectric layer where the first dielectric layer overlies the first well, a second dielectric layer encircling the first dielectric layer, a drain region abutting one edge of the second dielectric…
Lateral DMOS transistor with a self-aligned drain region
Granted: November 30, 2004
Patent Number:
6825531
An LDMOS transistor includes a body region, a source region, a conductive gate, an alignment structure and a drain region. The conductive gate is insulated from the semiconductor layer by a dielectric layer and overlies the body region. The source region is formed in the body region and is formed self-aligned to a first edge of the conductive gate. The alignment structure is formed adjacent a second edge, opposite the first edge, of the conductive gate. The alignment structure has a…
Truncated power enhanced drift lateral DMOS device which includes a ground strap
Granted: November 23, 2004
Patent Number:
6822290
A method and system for providing a power enhanced lateral DMOS device is disclosed. The method system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.
Bi-directional bus level translator
Granted: November 23, 2004
Patent Number:
6822480
A circuit is provided to transfer data between a first data bus section operating on a first supply voltage and a second data bus section operating on a second, different supply voltage. The circuit includes a first circuit path and a second circuit path each coupled to receive a data signal from one data bus section and to drive the other data bus section. Each of the first and second circuit paths includes a delay circuit, a flip flop, a logic circuit providing an AND function and an…
Increasing switching speed of geometric construction gate MOSFET structures
Granted: November 16, 2004
Patent Number:
6818950
In cellular MOSFET transistor arrays using a geometric gate construction, deleterious inherent capacitance induced by the construction is substantially reduced by the use of plugs in between adjacent source regions of transistor source rows and adjacent drain regions of transistor drain rows of the array. Embodiments using field oxide, thicker step gate oxide, dielectric materials in a floating gate construction, and shallow trench isolation region plugs are described.
Box-in-box field-to-field alignment structure
Granted: November 9, 2004
Patent Number:
6815128
A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is…
Multi-layer film stack polish stop
Granted: November 9, 2004
Patent Number:
6815353
A method for improved dielectric polish control adjacent to device areas is described. This is particularly important for bipolar structures, although the method may be used for MOS structures as well. The method includes using highly selective methods for removing oxide layers and polish stop layers in a multi-layer film stack, providing an oxide edge step height that is substantially uniform regardless of the size of the adjacent device area. In one embodiment, the multi-film stack…
Bipolar junction transistor with reduced parasitic bipolar conduction
Granted: November 9, 2004
Patent Number:
6815800
A bipolar transistor includes an auxiliary diffusion region formed in the base region having a conductivity type opposite to the base region and being electrically coupled to the base region. Alternately, the auxiliary diffusion region can be formed in the collector region where the auxiliary diffusion region has a conductivity type opposite to the collector region and is electrically coupled to the collector region. The auxiliary diffusion region forms a secondary parasitic transistor…
Integrated power switch with current limit control and a method of use
Granted: November 9, 2004
Patent Number:
6816349
An integrated power switch is disclosed. The power switch comprises a power transistor for providing an output current. The power transistor includes a grounded body. The power switch includes a sense transistor coupled to the power transistor. The sense transistor includes a floating body. The power switch further includes a resistor coupled to the floating body of the sense transistor. A value of the resistor is chosen such that the output current is regulated at a predetermined level.…
Load sensing circuit for a power MOSFET switch
Granted: October 26, 2004
Patent Number:
6809560
A circuit for sensing a voltage across a power switch includes a transmission gate, a low pass filter and a comparator. The power switch is controlled by a control signal for turning the power switch on and off to generate a switching voltage at a first current handling terminal of the power switch. The transmission gate is turned on whenever the power switch is turned on to sample the voltage across the power switch when the power switch is turned on. The sampled voltage is filtered by…
Robust power-on meter and method
Granted: October 26, 2004
Patent Number:
6810347
A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a…
Method and system for providing a power lateral PNP transistor using a buried power buss
Granted: September 28, 2004
Patent Number:
6798041
A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 &mgr;m deep and…
Universal clock generator using delay lock loop
Granted: September 28, 2004
Patent Number:
6798266
A clock generator and method generates a plurality of clocks of different frequencies using a delay lock loop and a sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal. The sequencer receives the delayed clock signals and selects one the delayed clock signals at any moment…
Robust power-on meter and method using a limited-write memory
Granted: August 31, 2004
Patent Number:
6785191
A data word is used to represent the total amount of time duration or predefined events a device has experienced during its lifetime. The data word is incremented count by count while the device is powered on and each updated data word is backed up to a non-volatile memory. A two-version redundancy scheme is employed to ensure failsafe backup and restoration of the data word. At any time at least one valid version of the data word exists in the non-volatile memory. In another aspect, a…
