Electrostatic discharge protection circuit
Granted: May 2, 1995
Patent Number:
5412527
A circuit which protects against damage to an integrated circuit caused by electrostatic discharge (ESD) includes a resistor connected at one end to an input pad, and a pair of back-to-back Schottky diodes connected to the other end of the resistor. The cathodes of the Schottky diodes are connected to each other by a common semiconductor substrate and connected to a supply voltage. The anode of one of the Schottky diodes is grounded, and the anode of the other Schottky diode is connected…
Capacitor and resistor connection in low voltage current source for splitting poles
Granted: April 25, 1995
Patent Number:
5410242
One embodiment of this invention provides an improved version of an existing current source circuit. A reduction in die size of the current source is achieved by modifying the circuit to enable a reduction in the capacitance of its feedback capacitor while improving the frequency compensation of its feedback loop. The modification changes the location of the dominant pole in the circuit and utilizes Miller multiplication to increase the effect of the feedback capacitor. The modification…
Current driver with shutdown circuit
Granted: April 11, 1995
Patent Number:
5406130
A circuit in accordance with the present invention includes a current driver circuit whose drive current is sensed by a threshold circuit. The threshold circuit, upon detecting an excess of current through the current driver circuit, controls a shutdown circuit for shutting down the current driver circuit. In the preferred embodiment, the shutdown circuit portion includes a delay circuit which prevents normal transient current spikes from triggering the shutdown circuit.
MOS transistor having increased gate-drain capacitance
Granted: March 14, 1995
Patent Number:
5397715
A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is desired to form p+ drain regions. A deep p.sup.+ drain region is then formed in the surface of the substrate so as to have a large diffusion under the polysilicon layer. This large diffusion results in a high gate-drain capacitance. The…
Bipolar transistor structure using ballast resistor
Granted: December 20, 1994
Patent Number:
5374844
A transistor structure incorporates a polysilicon layer which is doped with N-type dopants and is used as an emitter ballast resistor in an array of NPN transistors. In one embodiment, the polysilicon layer is also used as a diffusion source to form N-type emitter regions within a deep and high resistivity P-well, which acts as a relatively high value base ballast resistor for the transistor. In another embodiment, a standard base is used, contributing little base ballast resistance. A…
Diamond shaped gate mesh for cellular MOS transistor array
Granted: October 11, 1994
Patent Number:
5355008
A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and…
Method for forming PNP and NPN bipolar transistors in the same substrate
Granted: October 19, 1993
Patent Number:
5254486
In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for the PNP transistor is self-aligned with the base region of the NPN transistor. All the defined regions are then doped to achieve a desired base region concentration. A next masking step forms a layer of resist over the base region, and…
Integrated PNP power bipolar transistor with low injection into substrate
Granted: January 12, 1993
Patent Number:
5179432
In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P buried region acts as a catch diffusion for minority hole carriers injected into the epitaxial layer by the surface emitters that escape collection by the surface P+ collectors and which would otherwise be injected into the substrate. The N…
Semi self-aligned high voltage P channel FET
Granted: September 10, 1991
Patent Number:
5047820
An improved process to fabricate a high breakdown voltage MOSFET is disclosed. The process self-aligns the channel to the source and drain and semi self-aligns the gate electrode to the channel. The MOSFET also includes a boron field implant to extend the source and drain. A high voltage gate oxide can be provided.
Method for forming capacitor using FET process and structure formed by same
Granted: September 3, 1991
Patent Number:
5045966
A polysilicon or equivalent plate, to be used as an upper plate of the capacitor, is first formed over an oxide layer grown on a substrate. The length of the upper plate is made shorter than gate lengths of MOS transistors formed with the same process so that, after dopants are deposited into exposed regions of the substrate on both sides of the plate in a manner identical to forming self-aligned source and drain regions of an MOS transistor, the dopants will side-diffuse during drive-in…
Method for forming shorting contact for semiconductor which allows for relaxed alignment tolerance
Granted: July 23, 1991
Patent Number:
5034346
A method is disclosed for forming a shorting contact for shorting P-type and N-type conductivity regions in a semiconductor together. In one embodiment of this method, the P-type region is substantially a square and is surrounded by the N-type region. A substantially square contact opening is made to expose the P-type region and a portion of the N-type region. Sides of the contact opening are formed to be at substantially 45 degree angles with respect to sides of the substantially square…
Hidden zener diode structure in configurable integrated circuit
Granted: December 18, 1990
Patent Number:
4979001
In one embodiment of the invention, a P diffused region, acting as an anode of a zener diode, is formed within an N+ sinker which is part of a vertical transistor in a configurable integrated circuit. This N+ sinker contacts an N+ buried layer or an N+ substrate and provides an exposed contact region for the transistor. Conductivity types may, of course, be opposite to those described in this embodiment. In this way, an additional zener diode is made available to a user without requiring…
Diamond shorting contact for semiconductors
Granted: August 21, 1990
Patent Number:
4951101
A diamond-shaped short contact overlapping two differing conductivity regions in a semiconductor. The shape and orientation providing maximum alignment tolerances for a given size of contact opening.
Stacked multi-polysilicon layer capacitor
Granted: April 3, 1990
Patent Number:
4914546
A multilayer polysilicon structure is formed, where the various polysilicon layers and a conductive diffused region form plates of stacked capacitors, and electrodes contact each of the capacitor plates. The resulting capacitor structure inherently forms a series connected capacitor structure where each capacitor shares a plate with an adjacent capacitor. The structure is well suited for use in a voltage multiplier where each capacitor is charged to the supply voltage with the total…
