Linear peristaltic pump
Granted: November 9, 1999
Patent Number:
5980490
The invention relates to linear peristaltic pump of known contruction, in which a first cam (30a) and a first cam follower (11a) in the form of an input valve, at least three intermediate cams (30b-30e) and cam followers (11b-11e) for pumping operation and a last cam (30f) and a last cam follower (11f) in the form of an output valve are used.
Erasing method for a non-volatile memory
Granted: October 6, 1998
Patent Number:
5818763
The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps of: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel…
Resistor value control technique
Granted: July 14, 1998
Patent Number:
5779922
A resistivity map is prepared depicting the sheet resistance of a resistive film formed on a wafer as a function of position on the wafer. The resistivity map includes a plurality of zones each of which encompasses a specific range of resistivities of the resistive film. A mask containing numerous patterns which define associated resistors in the resistive film is divided into a plurality of zones which correspond to the plurality of zones of the resistivity map. One or more of the…
Method of forming a resistor having a serpentine pattern through multiple use of an alignment keyed mask
Granted: May 19, 1998
Patent Number:
5753391
Each die containing a resistive element which is to be trimmed has associated therewith a plurality of alignment targets. A cut mask having a trim pattern and an alignment key formed thereon is employed in a masking and etching step to trim the resistive element to a desired resistance. The number of links cut in the resistive element, and thus the final resistance thereof, depends on the particular positioning of the cut mask with respect to the die as determined by which of the…
Mask structure having offset patterns for alignment
Granted: May 5, 1998
Patent Number:
5747200
A structure and method are disclosed which allow for a more efficient use of silicon in a wafer fabrication process. In accordance with the present invention, the layout of masks used in the fabrication of circuit dice is modified by re-configuring the operating protocol of the stepper such that the alignment keys and targets are formed in the two subfields lying in the upper-left and upper-right corners, respectively, of each field. Thus, the 200 .mu.m-wide portion of each field…
Thermal shutdown circuit using a pair of scaled transistors
Granted: April 7, 1998
Patent Number:
5737170
The base of a thermal shutdown bipolar transistor having a V.sub.BE(on) which decreases with increasing temperature is biased with a bias voltage V.sub.PTATbias which increases proportionally with increasing absolute temperature. By supplying the base of the thermal shutdown transistor with a bias voltage V.sub.PTATbias which increases with increasing temperature rather than a bias voltage that remains constant or decreases with increasing temperature, the temperature at which the…
Circuit having trim pads formed in scribe channel
Granted: January 20, 1998
Patent Number:
5710538
In accordance with the present invention, trim pads used in trimming on-chip resistive elements are formed in the scribe channels interposed between respective dice on a wafer. Metal traces connect the trim pads to their associated resistive elements formed on the dice. Thus, each trim pad formed within the scribe channels results in a corresponding increase in the usable silicon surface area of the dice, thereby saving valuable silicon real estate.
PCMCIA power multiplexer integrated circuit with programmable decode
Granted: July 22, 1997
Patent Number:
5650973
A digital value on a plurality of control input terminals of a PCMCIA power multiplexer integrated circuit determines which one if any of a plurality of power input terminals (for example, 12 volts, 5 volts, and 3 volts) is coupled through the integrated circuit to a power output terminal. A decoder which decodes the digital value prevents any two of the power input terminals from being coupled to the power output terminal at the same time. The decoder is programmable so that a single…
MOS transistor having increased gate-drain capacitance
Granted: April 29, 1997
Patent Number:
5625216
A self-aligned MOS transistor is described in which the gate-drain underdiffusion length is substantially greater than the gate-source underdiffusion length, resulting in a relatively high gate-drain capacitance. This is accomplished by driving in the drain dopants to have a greater diffusion depth and underdiffusion length than that of the source dopants. The increased gate-drain capacitance obviates the need to provide a separate gate-drain capacitor where increased gate-drain…
Voltage regulator having MOS pull-off transistor for a bipolar pass transistor
Granted: April 1, 1997
Patent Number:
5617017
An improved output driver is disclosed having a pull-off diode-connected transistor and a resistor for keeping a pass transistor off when no load current is desired. An MOS transistor is coupled in parallel with the pull-off diode. As the input voltage increases beyond a threshold level, the diode is no longer able to pull-off the pass transistor's base due to increasing leakage currents in the pass transistor and is thus unable to turn off the pass transistor. The MOS transistor turns…
High value gate leakage resistor
Granted: December 31, 1996
Patent Number:
5589702
In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the…
Voltage regulator that operates in either PWM or PFM mode
Granted: October 22, 1996
Patent Number:
5568044
A switching voltage regulator achieves high efficiency by automatically switching between a pulse frequency modulation (PFM) mode and a pulse-width modulation (PWM) mode. Switching between the modes of voltage regulation is accomplished by monitoring the output voltage and the output current, wherein the regulator operates in PFM mode at small output currents and in PWM mode at moderate to large output currents. PFM mode maintains a constant output voltage by forcing the switching device…
Self-alignment technique for forming junction isolation and wells
Granted: September 17, 1996
Patent Number:
5556796
A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated,…
High voltage lateral DMOS device with enhanced drift region
Granted: May 14, 1996
Patent Number:
5517046
A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal…
PCMCIA power interface
Granted: May 7, 1996
Patent Number:
5514995
An improved power interface device suitable for managing power for a PCMCIA card is disclosed which includes internal charge pumps, to gradually turn on the device's internal N-channel MOSFETs, and a first discharge circuit for gradually turning off the N-channel MOSFETs. The first discharge circuit includes an MOS capacitor that incrementally discharges the gates of the N-channel MOSFETs such that the turn-off speed of each N-channel MOSFET is controlled by the ratio of the capacitances…
Switching regulator having high current prevention features
Granted: March 26, 1996
Patent Number:
5502610
A switching circuit has a pull-up FET and a pull-down FET coupled to a load circuit, each FET having a control terminal coupled to a current regulating circuit. The current regulating circuit provides a high predetermined current for a relatively short duration to the gates of the FETs to quickly turn on or turn off the FETs. After the short duration, a low quiescent current is applied to the gates to maintain the FETs in their present states. An inhibiting circuit, coupled between the…
Method of making a diamond shaped gate mesh for cellular MOS transistor array
Granted: September 5, 1995
Patent Number:
5447876
A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and…
Mask having multiple patterns
Granted: August 8, 1995
Patent Number:
5439764
One embodiment of the invention includes multiple patterns on a single mask, where all the patterns on the single mask are used for forming a single product. In the preferred embodiment, each of four quadrants of a mask have a different process layer pattern, where each of the four patterns is associated with a different process layer for the same product. After exposure of the wafer using the mask, the mask is rotated 90.degree. for the next exposure step so that the mask pattern image…
High value gate leakage resistor
Granted: August 8, 1995
Patent Number:
5439841
In a preferred embodiment, a diffused leakage resistor of a high value between approximately 200K ohms and 5M ohm is formed proximate to an MOS power transistor on the same silicon chip. The manufacturer of the chip has the option, using a mask, to connect or not connect the dedicated leakage resistor between the transistor's source and gate during the fabrication of the chip. The resistor is formed using the same masking steps already used to form the MOS transistor. To increase the…
Field effect transistor with switchable body to source connection
Granted: July 4, 1995
Patent Number:
5430403
To avoid forward biasing the diodes within an N-channel transistor, the body and source of the N-channel transistor are switchably connected via a high-voltage FET. The gates of the N-channel transistor and high-voltage transistor are connected together so that both transistors are on or off simultaneously. When both transistors are on, the high-voltage transistor shorts the body and source of the N-channel transistor. When both transistors are off, the body and source of the N-channel…
