Adaptive decoder for decoding an asynchronous data stream
Granted: May 12, 2009
Patent Number:
7533326
A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the incoming data stream using the information describing the incoming data stream. The best-fit bit analysis block is operative to find a pattern of data bits that best matches…
Laser turn-on accelerator independent of bias control loop bandwidth
Granted: May 12, 2009
Patent Number:
7532653
An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly.…
LED controller IC using only one pin to dim and set a maximum LED current
Granted: May 5, 2009
Patent Number:
7528555
An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal…
Input/output circuit for handling unconnected I/O pads
Granted: April 14, 2009
Patent Number:
7519890
A method based on a circuit coupled to an input-output bond pad (I/O pad) in an integrated circuit including an input buffer, an output buffer and a pad management circuit. The pad management circuit receives a first data signal, a first output enable signal, and a configuration signal indicative of the connection state of the I/O pad, and generates a second data signal and a second output enable signal. When the configuration signal indicates the I/O pad is to be connected to a package…
Method for fabricating non-volatile memory cells
Granted: April 7, 2009
Patent Number:
7514318
A method for fabricating non-volatile memory cells is provided. The method includes providing a substrate, forming a first dopant region in the substrate, forming a second dopant region in the first dopant region, growing a first isolation region over a first portion of the substrate, the first dopant region, and the second dopant region, growing a second isolation region over a second portion of the substrate, the first dopant region, and the second dopant region, defining a contact…
DC-DC converter recycling leakage inductor losses via auxiliary DC regulator
Granted: March 31, 2009
Patent Number:
7511972
A technique performed by a transformer-coupled DC-DC converter is described for recovering energy, due to leakage inductance in the transformer. A main power supply, providing a power supply voltage to a Vin terminal, is intermittently coupled to the primary winding of the transformer by a switching transistor. When the switching transistor is turned off, creating a voltage spike in the primary winding due to leakage inductance, the spike is conducted by a forward biased diode and…
Dual input prioritized LDO regulator
Granted: March 24, 2009
Patent Number:
7508179
An LDO regulator includes two linear regulator circuits and an internal priority logic scheme that favors generating a regulated output voltage using a regulated supply voltage over an unregulated supply voltage. The unregulated supply voltage is applied to a first input terminal from a raw voltage source. The regulated supply voltage is applied to a second input terminal from, for example, a switching (e.g., BUCK) regulator. Two output devices are respectively connected between the…
Laser controller integrated circuit including variable resolution data processing device
Granted: March 24, 2009
Patent Number:
7508329
A device for processing a digital input value includes a first memory portion having stored thereon Q delimiter values where the Q delimiter values divide the range of the N-bit digital input value into Q+1 regions and at least a first region and a second region are of unequal sizes, a second memory portion has stored thereon a look-up table storing Q+1 sets of coefficients for performing numerical value conversion of the digital input value to a digital output value in a second, natural…
Relay switch including an energy detection circuit
Granted: March 17, 2009
Patent Number:
7504748
A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to…
LDO regulator with ground connection through package bottom
Granted: March 10, 2009
Patent Number:
7501693
A low dropout (LDO) regulator device includes an LDO regulator integrated circuit housed in a 4-pin quad flat no-lead (QFN) package where the exposed die paddle is used as the ground terminal. The LDO regulator integrated circuit is formed on a semiconductor substrate. The 4-pin QFN package includes four perimeter lands connected to the input terminal, the output terminal, the enable terminal and the bypass terminal of the LDO regulator integrated circuit. The die paddle is to be…
LDO with slaved switching regulator using feedback for maintaining the LDO transistor at a predetermined conduction level
Granted: February 24, 2009
Patent Number:
7495420
A voltage regulator is disclosed having a switching regulator portion and an LDO regulator portion on a single chip. The switching portion switches one or more transistors at a high frequency to supply a voltage to a terminal of a series transistor of an LDO regulator. A second terminal of the series transistor provides the output voltage of the LDO regulator. The LDO regulator controls the conductivity of the series transistor to regulate the LDO regulator output voltage to be a desired…
Zero cost non-volatile memory cell with write and erase features
Granted: February 17, 2009
Patent Number:
7491605
A method for making a semiconductor structure of a memory device includes forming a capacitor having a gate dielectric between a gate conductor and a dopant region of a first conductivity type located in another dopant region of a second conductivity type, forming a bipolar transistor having a base region of the first conductivity type, and forming a field-effect transistor having a gate conductor coupled to the gate conductor of the capacitor, wherein the dopant region and the base…
Seal ring for mixed circuitry semiconductor devices
Granted: February 3, 2009
Patent Number:
7485549
In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
Constant on-time regulator with internal ripple generation and improved output voltage accuracy
Granted: January 27, 2009
Patent Number:
7482791
A buck switching regulator formed on an integrated circuit receives an input voltage and provides a switching output voltage on a switch output node using a constant on-time, variable off-time feedback control loop. The buck switching regulator includes an amplifier comparing a feedback voltage to a reference voltage and generating an output voltage on an output terminal, a first capacitor and a first resistor connected in series between the switch output node and the output terminal of…
Ripple generation in buck regulator using fixed on-time control to enable the use of output capacitor having any ESR
Granted: January 27, 2009
Patent Number:
7482793
A buck switching regulator formed on an integrated circuit and receives an input voltage and provides a switching output voltage on a switch output node using a fixed on-time, minimum off-time feedback control scheme. The buck switching regulator includes a first capacitor and a first resistor formed on the integrated circuit where the first capacitor and the first resistor are connected in series between the switch output node and a feedback voltage node, and a second capacitor coupled…
Look-up table expansion method
Granted: January 27, 2009
Patent Number:
7483426
A look-up table includes a first table formed using a first portion of the table entries where each table entry is associated with a look-up address and includes one or more key-data value pairs and an expansion pointer field, and a second table formed using a second portion of the table entries where each table entry is associated with an expansion address and includes one or more key-data value pairs. An expansion pointer field in a first table entry in the first table identifies a…
Method for forming Schottky diodes and ohmic contacts in the same integrated circuit
Granted: January 20, 2009
Patent Number:
7479444
A method for forming an ohmic contact and a Schottky diode in an integrated circuit includes providing a semiconductor substrate; forming first and second diffusion regions in the semiconductor substrate; forming an insulating layer on the semiconductor substrate; forming a first contact opening in the insulating layer and over the first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming…
Fully integrated All-CMOS AM transmitter with automatic antenna tuning
Granted: January 6, 2009
Patent Number:
RE40620
A monolithic AM transmitter is disclosed. An external antenna forms part of a resonance network so that the antenna resonance point is automatically tuned to the transmit frequency. This provides flexibility with no added cost to the transmitter. Additionally, components of the transmitter can be formed on a single monolithic integrated circuit.
Extending the voltage operating range of boost regulators
Granted: December 30, 2008
Patent Number:
7471071
One embodiment of the invention is a hybrid boost regulator that includes a conventional boost regulator chip that operates when its input voltage is above 2.5 volts and a pre-boost circuit that operates when its input voltage is above 1 volt. A single 1.5 volt battery may be used to power the hybrid boost regulator. The pre-boost circuit is connected to the voltage input terminal of the boost regulator chip. The pre-boost circuit boosts the battery voltage (e.g., 1.5v) at an output…
Flash memory cell transistor with threshold adjust implant and source-drain implant formed using a single mask
Granted: December 9, 2008
Patent Number:
7462543
A method for forming an NMOS transistor for use in a flash memory cell on a P-type semiconductor structure includes forming a photoresist layer over the semiconductor structure and patterning the photoresist layer using a source/drain mask for the NMOS transistor; forming a first N-type region and a second N-type region by a first implantation process using the patterned photoresist as an implant mask where the first implantation process uses a high implant dose at a low implant energy…
