Automatic external switch detection in synchronous switching regulator controller
Granted: January 12, 2010
Patent Number:
7646185
A synchronous switching regulator controller incorporates a switch detection circuit to determine the presence or absence of a power switch at the output of a switch driver so that the switch driver can be disabled when it is left unused. In one embodiment, the synchronous controller includes a switch detection circuit receiving a power cycle signal and the PWM ramp clock signal and measuring a voltage at an output node of the switch driver. The switch detection circuit provides a driver…
Method for forming zener zap diodes and ohmic contacts in the same integrated circuit
Granted: January 12, 2010
Patent Number:
7645691
A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact…
High efficiency linear regulator
Granted: December 29, 2009
Patent Number:
RE41061
A single chip hybrid regulator is disclosed having a first stage being a switching regulator and a second stage being a linear regulator. The switching regulator uses a filter circuit including an inductor and a capacitor. To make the hybrid regulator very small, the inductor value is selected so that the inductor saturates at a current level well below the maximum load current for the regulator. At low load currents, the small inductor does not saturate, and the regulated voltage…
Lateral double-diffused metal oxide semiconductor (LDMOS) device with an enhanced drift region that has an improved Rarea product
Granted: December 22, 2009
Patent Number:
7635621
A lateral double-diffused metal oxide semiconductor (LDMOS) device is disclosed. The LDMOS device comprises a gate region and a body region under the gate region. The LDMOS device includes an enhanced drift region under the gate region. The enhanced drift region touches the body region. By designing the device such that the enhanced drift region overlaps and compensates the lateral tail of the body region of the LDMOS transistor, the Ron*area product is reduced. Accordingly, the…
Relay switch including an energy detection circuit
Granted: December 22, 2009
Patent Number:
7635927
A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to…
Light emitting diode driver circuit with shunt switch
Granted: November 24, 2009
Patent Number:
7622871
A LED driver circuit avoids undesirable light generated by a LED due to leakage current by shunting the output terminal to the feedback terminal during periods when it is desired that the LED remain turned off. The shunting operation is achieved by providing a switch (e.g., a FET) that is connected between the output and feedback terminals of the LED, and is controlled by the user supplied reference signal. During active operation (i.e., when the user supplied reference signal is…
Generation of system power-good signal in hot-swap power controllers
Granted: November 24, 2009
Patent Number:
7624303
A power controller system is described herein, which may consist of one or more power controller ICs and other components. Each power controller selectively couples power supply voltages to a plurality of electrical devices, such as cards that have been inserted into expansion slots in a server. To simplify processing by a system processor monitoring the health of the power subsystem, each power controller IC asserts a power-good signal at a power-good terminal only if the operating…
LDMOS gate controlled schottky diode
Granted: October 27, 2009
Patent Number:
7608907
An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.
Threshold evaluation of EPROM cells
Granted: October 13, 2009
Patent Number:
7602646
Evaluating an embedded EPROM in a host IC device involves using program circuitry to program/unprogram all of the floating-gate cells of the embedded EPROM, then simultaneously transmitting a predetermined test bias voltage to all of the programmed/unprogrammed floating-gate cells, and then evaluating the output terminals of all of the floating-gate cells using a logic (e.g., wired NOR or NAND) circuit, whereby successful operation of all of the embedded EPROM cells causes the wired…
Hot-swap power controller generating sequenced power-good signals
Granted: September 15, 2009
Patent Number:
7590890
A power controller system is described herein, where a power-good signal (PWRGD) is asserted followed by a slightly delayed power-good signal (DLY_PWRGD) upon the system powering up. This PWRGD signal indicates that good power is being supplied to the card or other equipment, and the delayed signal tells a system processor that it is now ok to communicate with the card or other equipment. This delay allows the card or other equipment to reach a steady state condition before being…
Power FET with low on-resistance using merged metal layers
Granted: September 8, 2009
Patent Number:
7586132
In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is…
System for vertical DMOS with slots
Granted: August 18, 2009
Patent Number:
7576390
A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted…
Method of manufacturing NPN device
Granted: August 11, 2009
Patent Number:
7572707
A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device.
Transistors fabricated using a reduced cost CMOS process
Granted: August 11, 2009
Patent Number:
7573098
An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped…
Integrated circuit system for line regulation of an amplifier
Granted: July 14, 2009
Patent Number:
7560988
An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier.
Static address reservation protocol in a data network
Granted: June 30, 2009
Patent Number:
7554990
A method in a data network where the data network includes multiple terminal points interconnected by one or more network intermediate devices includes transmitting an invitation message from a first terminal point where the invitation message is broadcast through the data network to the multiple terminal points; in response to the invitation message, sending a reservation response message from a second terminal point where the reservation response message is broadcast through the data…
LED driver with fast open circuit protection, short circuit compensation, and rapid brightness control response
Granted: June 23, 2009
Patent Number:
7550934
An LED driver drives one or more strings of series-connected LEDs. A feedback voltage at a sense resistor is detected by an op amp, and the op amp controls the conductivity of a MOSFET in series with the LEDs to regulate the peak current. The MOSFET is also controlled by a PWM brightness control signal to turn the LEDs on and off at the PWM duty cycle. A boost regulator provides an output voltage to the string of LEDs. A divided voltage at the end of the string of LEDs is regulated by…
Method for providing a programmable electrostatic discharge (ESD) protection device
Granted: June 2, 2009
Patent Number:
7541235
A method for providing a programmable electrostatic discharge (ESD) protection device is provided. The method includes providing a source diffusion in a substrate, providing a deeper body diffusion in the substrate, providing a gate at a space between the source diffusion and the body diffusion, and providing a variable structure for shorting the source diffusion and the body diffusion to each other when ESD voltage is encountered on a circuit connected thereto, wherein the variable…
MOSFET triggered current boosting technique for power devices
Granted: June 2, 2009
Patent Number:
7541796
A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.
Detection of presence or absence of AC maintain power signature in power-over-ethernet system
Granted: May 12, 2009
Patent Number:
7532017
An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense…
