POWER SUPPLY FOR RING-OSCILLATOR BASED TRUE RANDOM NUMBER GENERATOR AND METHOD OF GENERATING TRUE RANDOM NUMBERS
Granted: July 16, 2015
Application Number:
20150199176
A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.
SYSTEM AND METHOD FOR PIXEL DATA COMPRESSION
Granted: July 16, 2015
Application Number:
20150201219
A system for, and method of, pixel data compression and a smartphone incorporating the system or the method. In one embodiment, the system includes: (1) a differential pulse code modulation encoder operable differentially to compress the two pixel values losslessly to yield two losslessly compressed pixel values and (2) an entropy encoder coupled to the differential pulse code modulation encoder and configured to receive and entropy-encode the losslessly compressed pixel values using a…
INPUT RAIL DYNAMIC POWER BALANCING AND MERGING
Granted: July 16, 2015
Application Number:
20150200541
A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by…
INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE
Granted: July 16, 2015
Application Number:
20150200020
An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks…
SRAM WRITE DRIVER WITH IMPROVED DRIVE STRENGTH
Granted: July 16, 2015
Application Number:
20150200006
A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the…
HARDWARE SUPPORT FOR DISPLAY FEATURES
Granted: July 16, 2015
Application Number:
20150199833
One embodiment of the present invention sets forth a system for displaying images including a hardware display controller engine that receives a rendered image. The system also includes an output compositor that composites a first image and the rendered image to create a second composited image. Finally, the system includes a display to display the second composited image.
PCIE CLOCK RATE STEPPING FOR GRAPHICS AND PLATFORM PROCESSORS
Granted: July 16, 2015
Application Number:
20150199822
Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction…
FLOORPLAN ANNEAL USING PERTURBATION OF SELECTED AUTOMATED MACRO PLACEMENT RESULTS
Granted: July 16, 2015
Application Number:
20150199464
A method of designing a floorplan for an integrated circuit comprises executing one or more automated placement processes on one or more seed floorplans to generate at least one output floorplan for each of the one or more seed floorplans, wherein the one or more automated placement processes are included in a plurality of pre-selected automated placement processes. The method further comprises computing a quality score for each output floorplan and, based on the quality scores,…
METHOD AND SYSTEM FOR IMPLEMENTING MULTI-STAGE TRANSLATION OF VIRTUAL ADDRESSES
Granted: July 16, 2015
Application Number:
20150199280
A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit…
APPROACH TO PREDICTIVE VERIFICATION OF WRITE INTEGRITY IN A MEMORY DRIVER
Granted: July 16, 2015
Application Number:
20150199223
A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares…
AUTOMATIC PROXIMITY DISPLAY SWITCHING FOR A MIRACAST ENVIRONMENT
Granted: July 16, 2015
Application Number:
20150199165
A proximity display system includes a mobile device that is enabled for Miracast sourcing and that provides a screen display. The proximity display system also includes a plurality of display units, which is enabled for Miracast sinking and is also coupled to the mobile device. Additionally, the proximity display system further includes a proximity sensing unit, which is coupled to the plurality of display units and enables a presentation of the screen display on a selected one of the…
VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT
Granted: July 9, 2015
Application Number:
20150192942
A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a…
METHOD AND SYSTEM FOR KEYFRAME DETECTION WHEN EXECUTING AN APPLICATION IN A CLOUD BASED SYSTEM PROVIDING VIRTUALIZED GRAPHICS PROCESSING TO REMOTE SERVERS
Granted: July 9, 2015
Application Number:
20150194136
A method for switching, including initializing an instantiation of an application and performing graphics rendering to generate a plurality of rendered frames through execution of the application in order to generate a first video stream comprising the plurality of rendered frames. The method includes sequentially loading the plurality of rendered frames into one or more frame buffers, and determining when a first bitmap of a frame that is loaded into a corresponding frame buffer matches…
DC BALANCING TECHNIQUES FOR A VARIABLE REFRESH RATE DISPLAY
Granted: July 9, 2015
Application Number:
20150194111
A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame…
TECHNIQUE FOR PROJECTING AN IMAGE ONTO A SURFACE WITH A MOBILE DEVICE
Granted: July 9, 2015
Application Number:
20150193915
A mobile device includes a projector configured to project images onto a target surface that resides within a projectable area. The mobile device identifies the target surface within the projectable area and then tracks that target surface as the mobile device is subject to different types of motion, including translation and rotation, among others. The mobile device then compensates for that motion when projecting the images, potentially eliminating distortion in the projected images.…
EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE
Granted: July 9, 2015
Application Number:
20150193907
A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The…
EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE
Granted: July 9, 2015
Application Number:
20150193903
A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The…
Prioritized Memory Reads
Granted: July 9, 2015
Application Number:
20150193358
A system includes a processing unit and a memory system coupled to the processing unit. The processing unit is configured to mark a memory access in the series of instructions as a priority memory access as a consequence of the memory access having a dependent instruction following less than a threshold distance after the memory access in the series of instructions. The processing unit is configured to send the marked memory access to the memory system.
EFFICIENCY IN A FUSED FLOATING-POINT MULTIPLY-ADD UNIT
Granted: July 9, 2015
Application Number:
20150193203
A four cycle fused floating point multiply-add unit includes a radix 8 Booth encoder multiplier that is partitioned over two stages with the compression element allocated to the second stage. The unit further includes an improved shifter design. Processing logic analyzes the input operands, detects values of zero and one, and inhibits portions of the processing logic accordingly. When one of the multiplicand inputs has a value of zero or one, the required multiplication becomes trivial,…
METHOD AND APPARATUS FOR BUFFERING SENSOR INPUT IN A LOW POWER SYSTEM STATE
Granted: July 9, 2015
Application Number:
20150193062
A solution is proposed for processing input in a lower power user interface of touch-sensitive display panels. According to an embodiment, a mobile computing device is placed in the low power mode. During this mode, the sensor controller produces a raw event/interrupts on a detected touch. Upon detecting a touch, the sensor controller also automatically increases the scan rate of the touch sensor, while the triggered event or interrupt proceeds to wake the system into a higher power…
