ON-DEVICE DATA COMPRESSION TO INCREASE SPEED AND CAPACITY OF FLASH MEMORY-BASED MASS STORAGE DEVICES
Granted: September 21, 2006
Application Number:
20060212645
A mass storage device having at least one flash memory device and DRAM or SRAM-based cache within a package, and which comprises co-processor means within the package for performing compression and decompression of cached data before writing the cached data to the flash memory device.
METHOD FOR INCREASING FREQUENCY YIELD OF MEMORY CHIPS THROUGH ON-CHIP OR ON-MODULE TERMINATION
Granted: March 16, 2006
Application Number:
20060056215
A memory module adapted for installation in an open memory socket on a mainboard of a computer. The memory module includes a substrate with an edge connector comprising pins along an edge of the substrate, and at least one memory package mounted to the substrate and containing a memory die electrically connected to input/output leads located along the perimeter of the memory package and through which data signals are transmitted to and from the memory die. Data signal lines electrically…
METHOD AND APPARATUS FOR INCREASING COMPUTER MEMORY PERFORMANCE
Granted: December 1, 2005
Application Number:
20050266711
A method and apparatus for providing power to a memory array of a computer's memory subsystem, and more particularly power at a level greater than that available through the computer motherboard so as to boost memory performance and operational stability. The apparatus includes a supply device for supplying an input voltage to the memory subsystem at a level that is higher than the power level provided to the memory subsystem by the motherboard. The method entails electrically connecting…
METHOD FOR INCREASING STABILITY OF SYSTEM MEMORY THROUGH ENHANCED QUALITY OF SUPPLY POWER
Granted: October 13, 2005
Application Number:
20050226076
An apparatus for buffering power transients in a supply power for expansion cards inserted into expansion slots on a computer motherboard. The apparatus comprises a printed circuit board, a connector on the printed circuit board, and at least one capacitor on the printed circuit board. The connector is configured to fit into one of the expansion slots on the motherboard, and comprises at least one power pin and at least one ground pin. The at least one capacitor is connected to the power…
POSTED PRECHARGE AND MULTIPLE OPEN-PAGE RAM ARCHITECTURE
Granted: April 14, 2005
Application Number:
20050078506
A method and architecture that overcomes the problem of latency-caused performance degradation of electronic memory systems. The method involves a “Posted Precharge,” by which an external command for Precharge is given as early as possible, such as immediately following a Read command. The execution of the Precharge is delayed by a precharge counter until all Read/Write commands are completed. By posting a precharge command on a bus at the first available opportunity, multiple pages…
