CONNECTOR ASSEMBLY AND METHOD FOR SATA DRIVES
Granted: March 3, 2011
Application Number:
20110053429
A connector assembly and method suitable for making data and power connections with mass storage devices that use the SATA interface standard. The connector assembly includes a connector having a pair of oppositely-disposed surfaces, a face between the surfaces, and data and power connector portions disposed in the face. The data and power connector portions are adapted to establish data and power connections between the connector and a SATA interface of a mass storage device. The…
OPTICAL MEMORY DEVICE AND METHOD THEREFOR
Granted: February 24, 2011
Application Number:
20110044086
A nonvolatile memory device and method using phase changes in a substrate to alter optical properties of the substrate for the purpose of data storage. The memory device includes a substrate containing a phase change material having phases comprising amorphous and crystalline phases. The phase change material has optical properties that change depending on whether the phase change material is in the amorphous phase or the crystalline phase. The memory device is further equipped with one…
METHODS, SYSTEMS AND DEVICES FOR INCREASING DATA RETENTION ON SOLID-STATE MASS STORAGE DEVICES
Granted: February 24, 2011
Application Number:
20110047322
Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices.
NAND FLASH-BASED STORAGE DEVICE WITH BUILT-IN TEST-AHEAD FOR FAILURE ANTICIPATION
Granted: February 24, 2011
Application Number:
20110047421
A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number…
ON-DEVICE DATA COMPRESSION FOR NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES
Granted: January 6, 2011
Application Number:
20110004728
A non-volatile memory-based mass storage device that includes a host interface attached to a package, at least one non-volatile memory device within the package, a memory controller connected to the host interface and adapted to access the non-volatile memory device in a random access fashion through a parallel bus, a volatile memory cache within the package, and co-processor means within the package for performing hardware-based compression of cached data before writing the cached data…
HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD
Granted: December 23, 2010
Application Number:
20100325352
A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second…
METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES
Granted: December 9, 2010
Application Number:
20100312953
A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode…
MASS STORAGE DEVICE FOR A COMPUTER SYSTEM AND METHOD THEREFOR
Granted: November 25, 2010
Application Number:
20100296236
A method and mass storage device that combine multiple solid state drives (SSDs) to a single volume. The device includes a carrier board and at least two solid state drives having power and data connections to the carrier board. The carrier board includes a circuit board functionally connected to a control logic and at least two secondary connectors that are disposed at different edges of the circuit board and functionally connected to the control logic. The solid state drives are…
METHOD AND APPARATUS FOR THERMAL MANAGEMENT OF COMPUTER MEMORY MODULES
Granted: November 25, 2010
Application Number:
20100296240
A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior…
MODULAR MASS STORAGE SYSGTEM AND METHOD THEREFOR
Granted: September 23, 2010
Application Number:
20100241799
A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to…
MEMORY MODULES AND METHODS FOR MODIFYING MEMORY SUBSYSTEM PERFORMANCE
Granted: June 10, 2010
Application Number:
20100142247
Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from…
METHOD AND APPARATUS FOR USING BIOPOTENTIALS FOR SIMULTANEOUS MULTIPLE CONTROL FUNCTIONS IN COMPUTER SYSTEMS
Granted: March 18, 2010
Application Number:
20100069780
A biosignal-computer-interface apparatus and method. The apparatus includes one or more devices for generating biosignals based on at least one physiological parameter of an individual, and a computer-interface device capable of performing multiple tasks, including converting the biosignals into at least one input signal, establishing a scale encompassing different levels of the input signal, multiplying the input signal into parallel control channels, dividing the scale into multiple…
METHOD FOR OPTIMIZING MEMORY MODULES FOR USER-SPECIFIC ENVIRONMENTS
Granted: February 5, 2009
Application Number:
20090037900
A method for altering and preferably optimizing the performance of system memory of a computer system. The method includes identifying the motherboard and the memory module of the computer system, and then searching multiple SPD update files associated with multiple motherboards and containing data corresponding to physical and operational characteristics of multiple memory modules. From these SPD update files, a compatible SPD update file is identified that is compatible with the…
WIRELESS COMPUTER MOUSE WITH BATTERY SWITCHING CAPABILITY
Granted: January 8, 2009
Application Number:
20090009475
A wireless mouse suitable for use with a computing device, and method of using such a mouse. The mouse includes a housing, electronics within the housing for sensing movement of the mouse and wirelessly communicating with the computing device, at least two batteries within the housing, a device for monitoring a power level of each of the batteries, and a device for switching between the batteries to deliver electrical power from one of the batteries to the electronics. Each battery is…
METHOD AND APPARATUS FOR COOLING COMPUTER MEMORY
Granted: November 27, 2008
Application Number:
20080291630
A method and apparatus for cooling chips on a computer memory module. The apparatus includes a primary and secondary heat spreaders, at least a first heatpipe coupled to the primary heat spreader and having a remote portion spaced apart from the primary heat spreader and thermally contacting the secondary heat spreader, and a coolant within the first heatpipe and the primary heat spreader so as to absorb heat from the primary heat spreader and conduct the heat to the secondary heat…
IEEE 1394 INTERFACE-BASED FLASH DRIVE USING MULTILEVEL CELL FLASH MEMORY DEVICES
Granted: September 11, 2008
Application Number:
20080222349
A flash drive and method of transferring data from a system to a flash drive. The flash drive includes a casing, a plurality of flash memory devices within the casing, each of the flash memory devices having multilevel cells, an IEEE 1394 interface controller within the casing, coupled to the flash memory devices, and interfacing with the flash memory devices for interleaved multichannel access to and from at least two of the flash memory devices, and at least one IEEE 1394 interface…
METHOD AND SYSTEM FOR MONITORING POWER CONSUMPTION OF A COMPUTER COMPONENT
Granted: May 15, 2008
Application Number:
20080115001
A system (10) and method for monitoring power consumption of a computer system component, such as a central processing unit (CPU), of a desktop computer system. The component is supplied with supply power from a power supply unit (22) of the computer through a power supply cable (14). A coupling (12) is disposed between the power supply unit (22) and a substrate (e.g., motherboard) on which the component is mounted, and is electrically connected to at least one power supply line (18) of…
GAMING HEADSET WITH INTEGRATED MICROPHONE AND ADAPTED FOR OLFACTORY STIMULATION
Granted: February 28, 2008
Application Number:
20080049960
A gaming headset adapted for precise delivery of chemical substances capable of olfactory stimulation, such as odorants, fragrances, pheromones, etc. The headset includes at least one earpiece containing a speaker, a feature for securing the earpiece to the person's head while positioning the speaker over one of the person's ears when the headset is worn, an armature disposed relative to the earpiece so as to extend toward the person's mouth, a microphone located on the armature so as to…
METHOD AND APPARATUS FOR THERMAL MANAGEMENT OF COMPUTER MEMORY MODULES
Granted: July 12, 2007
Application Number:
20070159789
A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior…
INTEGRATED SRAM CACHE FOR A MEMORY MODULE AND METHOD THEREFOR
Granted: January 4, 2007
Application Number:
20070005902
A memory module having at least one random access memory device and a memory bus on a substrate. The memory module further comprises an SRAM cache interfaced with the random access memory device through an ASIC associated with the SRAM cache and operable as a prefetch controller for the SRAM cache. The ASIC and SRAM cache cooperate to enable data to be prefetched and cached during idle cycles of the memory device, thereby increasing the overall operating speed of the memory circuit by…
