Variable capacitor using MOS gated diode with multiple segments to limit DC current
Granted: September 21, 2004
Patent Number:
6794707
A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion…
Clock presence detector comparing differential clock to common-mode voltage
Granted: September 14, 2004
Patent Number:
6791369
Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each…
Power-down activated by differential-input multiplier and comparator
Granted: September 14, 2004
Patent Number:
6791371
A power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is applied to a multiplier, which generates a squared difference. The squared difference is smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage, either explicitly or implicitly, to detect when the voltage difference across the differential inputs is too small. A…
Dual-loop PLL with DAC offset for frequency shift while maintaining input tracking
Granted: July 13, 2004
Patent Number:
6762634
A phase-locked loop (PLL) keeps tracking a reference clock when a frequency offset is introduced. The PLL has primary and secondary PLL loops. A digital-to-analog converter (DAC) generates a current that is passed through an offset resistor to generate an offset voltage. An op amp is inserted in the primary loop between a filter capacitor and a voltage-controlled oscillator (VCO). The offset resistor is coupled between the inverting input of the op amp and the op amp's output. When…
Direct power-to-ground ESD protection with an electrostatic common-discharge line
Granted: June 29, 2004
Patent Number:
6756834
ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only…
Pin-to-pin ESD-protection structure having cross-pin activation
Granted: June 29, 2004
Patent Number:
6757147
A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor…
Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption
Granted: May 25, 2004
Patent Number:
6741111
A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are…
ESD-isolation circuit driving gate of bus-switch transistor during ESD pulse between two I/O pins
Granted: May 18, 2004
Patent Number:
6738242
A bus-switch transistor connects two I/O pins when an enable signal on its gate is activated. Each pin has an electro-static-discharge (ESD) protection devices. When the internal ground and the enable are floating, and an ESD pulse is applied between the two pins, an isolation circuit couples part of the ESD pulse to the gate of the bus-switch transistor, keeping the transistor turned off. This forces the ESD pulse to travel through the ESD protection devices, preventing damage to the…
Bus relay and voltage shifter without direction control input
Granted: April 20, 2004
Patent Number:
6724224
A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can…
Substrate-triggering of ESD-protection device
Granted: April 20, 2004
Patent Number:
6724592
Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus.…
Voltage booster with increased voltage boost using two pumping capacitors
Granted: February 17, 2004
Patent Number:
6693480
A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to…
Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages
Granted: February 17, 2004
Patent Number:
6693987
A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two…
Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations
Granted: February 10, 2004
Patent Number:
6690192
Edge rates for output driver transistors are increased for slower conditions such as caused by supply-voltage, temperature, and process variations. The edge rates are increased by increasing charging and discharging currents to the gates of the driver transistors. Process-sensing transistors have gates tied to power or ground. Current through the process-sensing transistors changes with supply-voltage, temperature, and process variations. The currents through process-sensing transistors…
Multi-port PCI-to-PCI bridge with combined address FIFOs but separate data FIFOs for concurrent transactions
Granted: February 10, 2004
Patent Number:
6691200
A multi-port Peripheral Component Interconnect (PCI) bus bridge allows for cascading of PCI buses and reduction of bus loading and traffic. The multi-port PCI bridge has three or more ports that connect to PCI buses. At each destination port, a pair of data FIFOs is provided for each source port, for read and write data. Each destination port has three address FIFOs, one for posted-memory-write (PMW) addresses, another for delayed-transaction-request (DTR) addresses and data, and a third…
Variable capacitor using MOS gated diode with multiple segments to limit DC current
Granted: January 6, 2004
Patent Number:
6674116
A voltage-variable capacitor uses the channel-to-substrate junction from a gated diode formed from a metal-oxide-semiconductor transistor. The transistor gate has at least two contacts that are biased to different voltages. The gate acts as a resistor with current flowing from an upper gate contact to a lower gate contact. The gate-to-source voltage varies as a function of the position. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion…
Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
Granted: January 6, 2004
Patent Number:
6674319
A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines. A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an…
Isolating circuit for P/N transmission gate during hot-plug insertion
Granted: December 30, 2003
Patent Number:
6670829
A bus switch has a p-channel and an n-channel transistor in parallel between two buses. When power is disconnected to the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel transistor. This biasing keeps the p-channel transistor turned off. A gate connecting p-channel transistor connects the hot bus to the p-channel gate node, while a substrate connecting p-channel transistor connects the hot bus to…
Latched active fail-safe circuit for protecting a differential receiver
Granted: November 18, 2003
Patent Number:
6650149
A fail-safe circuit for a differential receiver can tolerate noise. A latch is enabled when both differential inputs V+, V− rise above a reference voltage that is close to Vcc. The latch, once enabled, is set by an offset amplifier, signaling the fail-safe condition. The offset amplifier sets the latch when V+ is above or equal to V−. The differential amplifier has a small offset voltage to allow the latch to remain set when V+ and V− are equal in…
Internet ESD-shunt diode protected by delayed external MOSFET switch
Granted: October 28, 2003
Patent Number:
6639771
Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass…
Voltage-controlled crystal oscillator (VCXO) using MOS varactors coupled to an adjustable frequency-tuning voltage
Granted: September 30, 2003
Patent Number:
6628175
A voltage-controlled crystal oscillator (VCXO) has variable load capacitors on the crystal nodes. The variable load capacitors are p-channel or n-channel transistors with their source and drain nodes connected to a crystal node. The gates are driven by an input voltage that is generated from a full-swing control voltage by a voltage conversion circuit. The input voltage has a half-swing of only half of the power-supply voltage, or VDD/2. The input voltage driving n-channel capacitors…
