Live-insertion PMOS biasing circuit for NMOS bus switch
Granted: August 19, 2003
Patent Number:
6608517
A bus switch has an n-channel bus-switch transistor between two buses and a p-channel pullup transistor. When power is disconnected from the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel pullup transistor. This biasing keeps the p-channel transistor turned off. When power is off, a connecting p-channel transistor connects the higher voltage on the hot bus to the p-channel gate node, while an…
Power down mode signaled by differential transmitter's high-Z state detected by receiver sensing same voltage on differential lines
Granted: July 15, 2003
Patent Number:
6593801
A power-down signal is encoded into a differential pair of lines between two chips. When the differential transmitter powers down, it enters a high-impedance state and floats the differential lines A shunt resistor between a pair of differential lines equalize the voltages on the differential lines so they float to a same voltage when a differential transmitter is disabled and enters a high-impedance state. The condition of equal voltages on the differential lines is detected by an…
Low-voltage differential driver with opened eye pattern
Granted: July 8, 2003
Patent Number:
6590432
A differential output buffer has a primary stage and a secondary stage that each directly drive differential outputs. Link transistors between the secondary stage and the differential outputs are eliminated. The primary stage continuously receives differential inputs applied to gates of n-channel sourcing and sinking transistors. The sources of the sourcing transistors and the drains of the sinking transistors are connected to the true and complement differential outputs. The secondary…
Differential clock driver with transmission-gate feedback to reduce voltage-crossing sensitivity to input skew
Granted: June 24, 2003
Patent Number:
6583656
A differential clock driver uses feedback to reduce timing skews between the true and complement differential outputs. Each of the differential outputs has a pull-up driver and a pull-down driver. Each pull-up or pull-down driver has an initial transistor and a final transistor in parallel to drive the output. A resistor separates gates of the initial and final transistors, causing a delay to enable the final transistor. A transmission gate provides feedback from the other output to the…
Reduced clock-skew in a multi-output clock driver by selective shorting together of clock pre-outputs
Granted: June 24, 2003
Patent Number:
6583659
A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts…
Phase-locked loop (PLL) with mixer for subtracting outer-band phase noise
Granted: June 3, 2003
Patent Number:
6573769
A phase-locked loop (PLL) includes a final mixer on its output. The final mixer subtracts out a noise or error term from the PLL's output to reduce noise and jitter. A first mixer generates the error term by subtracting a feedback clock from the reference clock. This error term is near D.C. since the feedback and reference clocks are at the same frequency. When this error term is subtracted from the PLL output, a secondary maxima in the noise plot at the PLL's loop bandwidth is…
Bi-directional undershoot-isolating bus switch with directional control
Granted: May 6, 2003
Patent Number:
6559703
A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a…
Power down circuit detecting duty cycle of input signal
Granted: April 22, 2003
Patent Number:
6552578
When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is…
ESD-protection device with active R-C coupling to gate of large output transistor
Granted: April 22, 2003
Patent Number:
6552583
Large output driver transistors are used to shunt electro-static-discharge (ESD) pulses. ESD pulses are capacitivly coupled to the gates of the large driver transistors by R-C networks. The capacitive coupling causes a gate-to-source voltage to exceed the transistor threshold, turning on the large driver transistor to shunt the ESD current. Transistor switches are inserted into the R-C networks. These transistor switches disconnect the R-C networks during normal operation, and ensure…
Active Vcc-to-Vss ESD clamp with hystersis for low supply chips
Granted: April 22, 2003
Patent Number:
6552886
An electro-static-discharge (ESD) protection circuit is coupled between power and ground. It protects core circuits in a semiconductor chip. The ESD protection circuit is an active circuit that drives the gate of an n-channel clamp transistor. The clamp transistor shunts current from power to ground when its gate is driven high during an ESD event. A voltage divider generates a sense voltage that drives a first inverter. The sense voltage is normally much lower than the switch threshold…
MOS variable capacitor with controlled dC/dV and voltage drop across W of gate
Granted: April 1, 2003
Patent Number:
6541814
A voltage-variable capacitor is constructed from a metal-oxide-semiconductor transistor. The transistor source has at least two contacts that are biased to different voltages. The source acts as a resistor with current flowing from an upper source contact to a lower source contact. The gate-to-source voltage varies as a function of the position along the source-gate edge. A critical voltage is where the gate-to-source voltage is equal to the transistor threshold. A portion of the source…
Switched IOH and IOL current sources for CMOS low-voltage PECL driver with self-timed pull-down current boost
Granted: April 1, 2003
Patent Number:
6542031
A differential buffer/driver has a switch network that connects an IOH current source to a differential output to be drive high, and connects an IOL current source to the other differential output to be driven low. Each output can be connected to a pull-down boost current sink. A boost pulse momentarily connects a boost current sink to the differential output being driven low. The differential buffer generates a pair of boost pulses to activate the boost current for either differential…
Fail-safe circuit with low input impedance using active-transistor differential-line terminators
Granted: February 25, 2003
Patent Number:
6525559
A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node…
Spread-spectrum clock buffer/driver that modulates clock period by switching loads
Granted: December 31, 2002
Patent Number:
6501307
A clock modulator spreads the frequency spectrum of an input clock to generate an output clock. A capacitor is connected to an intermediate clock node by a load-switching transistor. When the transistor is turned on, the capacitor increases the loading on the intermediate clock node, increasing delay. When the transistor is turned off, the delay is reduced. Output clock cycle periods are extended when delay is added, and reduced when the transistor turns off. A counter or sequencer is…
Low-power substrate bias generator disabled by comparators for supply over-voltage protection and bias target voltage
Granted: November 26, 2002
Patent Number:
6486727
A substrate bias generator has a ring oscillator disabled when a supply over-voltage condition is detected by a supply comparator, or when a target substrate voltage is reached. A substrate comparator compares the substrate voltage to a reference generated by a p-channel sense transistor that is independent of the substrate voltage. The substrate is sensed by an n-channel sense transistor with only its bulk connected to the substrate voltage. Current sources for the sense transistors and…
Capacitively-coupled extended swing zero-DC-power active termination with CMOS overshoot/undershoot clamps
Granted: August 6, 2002
Patent Number:
6429678
An active terminating circuit has buffers to produce wider voltage drives on clamping transistors. A transmission line drives coupling capacitors. One capacitor drives an upper node that drives the gate of an upper buffer transistor. The upper buffer transistor drives a p-gate node coupled to a gate of a p-channel clamping transistor. The other capacitor drives a lower node that drives the gate of a lower buffer transistor, which drives an n-gate node of an n-channel clamping transistor.…
Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
Granted: July 30, 2002
Patent Number:
6426662
A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than…
CMOS low-voltage PECL driver with initial current boost
Granted: July 23, 2002
Patent Number:
6424217
A differential amplifier has a boosted sink current that is turned on by a pulse generator when the output is driven low. This boosted sink current quickly lowers the output to the voltage-output-low VOL level. After the pulse ends, the sink current ends and power is reduced to a lower standby level. A differential pair of switches receives the true and complement data. One switch is closed when the data is true, connecting a current source that sets the standby voltage-output-high VOH…
BiDirectional active voltage translator with bootstrap switches for mixed-supply VLSI
Granted: April 2, 2002
Patent Number:
6366124
A voltage translator programmably converts signals generated from a first power-supply voltage to a second power-supply voltage, or vice-versa. In response to control signals, bootstrap switches connect either the first or second power supply to a first internal supply, and either the second or first power supply to a second internal supply. A pair of inverters are sourced by the first power supply and generate true and complement data signals. Cross-coupled p-channel load transistors…
Reduced-undershoot CMOS output buffer with delayed VOL-driver transistor
Granted: March 19, 2002
Patent Number:
6359478
A large pull-down voltage-output-low VOL transistor is placed in parallel with a smaller pull-down switching transistor. The smaller switching pull-down transistor is turned on during switching. Once switching has nearly completed, the larger pull-down VOL transistor is turned on to provide a current sink for maintaining a VOL close to ground. Switching current is limited by the smaller switching pull-down transistor, while a large static sink current is provided by the VOL transistor to…
