Undershoot-isolating MOS bus switch
Granted: April 18, 2000
Patent Number:
6052019
A bus switch has an n-channel bus-switch transistor that connects an input-bus signal to an output bus. A gate protection circuit prevents undershoots on the inputs from coupling to the output when the bus switch isolates the buses. The gate of the bus-switch transistor is driven to ground during isolation mode. When a high-to-low transition of the input-bus signal is detected, a pulse generator generates a pulse. The pulse disconnects the gate from ground. A connecting n-channel…
Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder
Granted: April 11, 2000
Patent Number:
6049229
A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two…
Bus switch having both p- and n-channel transistors for constant impedance using isolation circuit for live-insertion when powered down
Granted: March 7, 2000
Patent Number:
6034553
A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the network card and a bus switch are in a powered down state. Although n-channel transistors are normally off when the power is off, p-channel transistors can conduct. The hot bus could be disturbed when the bus switch is first connected…
Noise supression using neighbor-sensing for a CMOS output buffer with a large DC current sink
Granted: October 5, 1999
Patent Number:
5963047
A CMOS output buffer has as pull-downs a smaller driver transistor and a larger driver transistor. Both transistors drive the output low in parallel initially during a voltage transition, but the larger transistor is disabled for the remainder of the output voltage swing when reflections and ringing occur. A pulse is generated by a transition detector when an input to the output buffer transitions low. The pulse generated disables the larger driver for a short period of time but later…
Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder
Granted: October 5, 1999
Patent Number:
5963053
A pseudo-emitter-coupled-logic (PECL) receiver has a wide common-mode range. Two current-mirror CMOS differential amplifiers are used. One amplifier has n-channel differential transistors and a p-channel current mirror, while the second amplifier has p-channel differential transistors and an n-channel current mirror. When the input voltages approach power or ground, one type of differential transistor continues to operate even when the other type shuts off. The outputs of the two…
Voltage booster with reduced Vpp current and self-timed control loop without pulse generator
Granted: August 31, 1999
Patent Number:
5946204
An n-channel bus switch has a transistor gate boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. No pulse generator is needed. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pullup transistor drives the boosted node from ground to Vcc. The pulse generator is eliminated by using a Schmidt-trigger to sense the voltage of the boosted node. Once the Schmidt-trigger senses that the voltage…
Twisted-pair driver with staggered differential drivers and glitch free binary to multi level transmit encoder
Granted: June 29, 1999
Patent Number:
5917340
A twisted-pair current driver is implemented in CMOS. EMI from sharp changes in the current driven is reduced by gradually changing the current driven when the inputs change. The current driver is divided into N differential drivers, each driving one-Nth of the total switching current to the twisted pair. Delay lines delay when input changes are sent to each of the four differential drivers, staggering their response. Either binary or multi-level-transition (MLT-3) data can be…
CMOS PECL driver with programmable current for varying voltage swings and termination types
Granted: February 23, 1999
Patent Number:
5874837
A differential-output current driver is constructed entirely of CMOS transistors. Pseudo-ECL levels are reached when a standard resistive termination is connected to the outputs. The current driver can also drive a non-standard termination to the PECL levels. The non-standard termination is low power because it does not draw standby current from power to ground. Current from the current sources within the current driver are assigned to either the switching current or the constant…
Voltage booster with pulsed initial charging and delayed capacitive boost using charge-pumped delay line
Granted: December 8, 1998
Patent Number:
5847946
A bus switch is constructed from an n-channel transistor. The gate terminal of the n-channel transistor is boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pulse is generated to drive the boosted node from ground to Vcc. The boosted node is also an input of a delay line. After a delay through the delay line, the pulsed pull-up is turned…
Parallel micro-relay bus switch for computer network communication with reduced crosstalk and low on-resistance using charge pumps
Granted: September 15, 1998
Patent Number:
5808502
A micro-relay replaces electromechanical and solid-state opto-isolated relays in a computer network. The micro relay is an integrated circuit containing several bus switches in parallel. Each bus switch can make or break a connection. The bus switch is an n-channel MOS transistor with the source and drain connected to different network busses. A bus enable input causes the connection to be made or broken. The bus enable input is separately buffered for each gate of each MOS transistor to…
Meta-stable-resistant front-end to a synchronizer with asynchronous clear and asynchronous second-stage clock selector
Granted: June 9, 1998
Patent Number:
5764710
A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that…
Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures
Granted: February 17, 1998
Patent Number:
5719427
A non-volatile memory cell uses a p+ diffusion region spaced a lateral distance from the n+ drain of the n-channel programmable transistor. A diode between this p+ diffusion and the n+ drain has a low breakdown voltage because of the close spacing of the high-doping n+ and p+ diffusions. This diode generates electrons when avalanche breakdown occurs. The avalanche electrons are swept up into the programmable gate during programming. Since the avalanche electrons are generated by the…
Packet-based dynamic de-skewing for network switch with local or central clock
Granted: February 17, 1998
Patent Number:
5719862
A network switch uses a simple switch core of analog MOS transistor switches. The switch core is surrounded by many media-access controllers (MAC's) which buffer the data through the switch core. Multiple connections through the switch core may be made between different pairs of MAC's. Just one signal path through the switch core is needed per connection as a second path through the switch core for the clock is not needed. The clock is not encoded with the data, so PLL's are not needed…
High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing
Granted: February 10, 1998
Patent Number:
5717343
A CMOS output buffer has a first stage with smaller driver transistors and a second stage having larger driver transistors. Both stages drive the output in parallel during the first half of a voltage transition, but the larger, second stage is disabled during the second half of the output voltage swing. The output voltage is fed back to an isolation circuit by a pulse generator which is triggered by the output reaching the switching threshold. The pulse generated disables the larger…
Programmable substrate bias generator with current-mirrored differential comparator and isolated bulk-node sensing transistor for bias voltage control
Granted: December 2, 1997
Patent Number:
5694072
A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing…
Frequency synthesizer with adaptive loop bandwidth
Granted: May 20, 1997
Patent Number:
5631587
A method for a frequency synthesizer with adaptive loop bandwidth is disclosed, which is adjusted by the improved frequency synthesizer includes a phase-locked loop and a phase-locked loop adjustment circuit. The phase-locked loop has loop characteristics including a loop bandwidth, a natural frequency, a damping factor, and the like. The phase-locked loop adjustment circuit is adjusted in response to a change in output frequency.
Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
Granted: February 11, 1997
Patent Number:
5602882
A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data…
Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network
Granted: March 26, 1996
Patent Number:
5502750
A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data…
All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages
Granted: August 22, 1995
Patent Number:
5444397
An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver…
