METHOD OF MAKING A HIGH-VOLTAGE TRANSISTOR WITH BURIED CONDUCTION REGIONS
Granted: October 24, 2002
Application Number:
20020153556
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state…
HIGH-VOLTAGE TRANSISTOR WITH BURIED CONDUCTION LAYER
Granted: October 24, 2002
Application Number:
20020153560
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
High-voltage transistor with buried conduction layer
Granted: October 24, 2002
Application Number:
20020153561
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
High-voltage transistor with buried conduction layer
Granted: October 17, 2002
Application Number:
20020149052
A lateral, high-voltage, FET having a low on-resistance and a buried conduction layer comprises a P-type buried layer region within an N-well formed in a P-type substrate. The P-type buried layer region is connected to a drain electrode by a first P-type drain diffusion region that is disposed in the N-well region. The P-type buried layer region is also connected to a second P-type drain diffusion region that extends down from the surface at one end of the PMOS gate region. A P-type…
Off-line converter with digital control
Granted: September 26, 2002
Application Number:
20020136035
A DC to DC converter comprising an energy storage element comprising an energy storage element input and an energy storage element output, the energy storage element input coupled to receive a first power level and the energy storage element output providing a second power level. The converter also comprises a feedback circuit comprising a feedback input and a feedback output, the feedback input coupled to the energy storage element output. The converter further comprises a regulator…
METHOD OF FABRICATING A HIGH-VOLTAGE TRANSISTOR
Granted: September 19, 2002
Application Number:
20020132405
A method for making a high voltage insulated gate field-effect transistor with one or more JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first epitaxial layer of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. A second epitaxial layer is formed on the first epitaxial layer and the implant process repeated to form a second plurality of buried layers in stacked…
High-voltage transistor with JFET conduction channels
Granted: September 19, 2002
Application Number:
20020132406
A high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises a first buried layer disposed in a first epitaxial layer formed on a substrate, a second buried layer disposed in a second epitaxial layer formed on the first epitaxial layer, with the first and second buried layers being spaced vertically apart in a substantially parallel configuration such that a JFET conduction channel of the first conductivity type is formed between the first and…
Method of fabricating a high-voltage transistor
Granted: August 29, 2002
Application Number:
20020119611
A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of…
High-voltage transistor with multi-layer conduction region
Granted: May 9, 2002
Application Number:
20020053698
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state…
High-voltage transistor with multi-layer conduction region
Granted: May 2, 2002
Application Number:
20020050613
A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state…
