Protocol for Transmission of Data Over a Communication Link
Granted: August 23, 2012
Application Number:
20120215952
Video data is transmitted from a video source to a video sink via a fixed rate serial link with a substantially constant unit interval for transmission of each symbol of the encoded data. The unit interval of the serial link is maintained substantially constant, and does not vary regardless of the display parameters of the video data. The video data is encoded into a plurality of video data streams, with each data stream including a plurality of fields. The fields include at least a…
Systems and methods for control of receivers
Granted: August 23, 2012
Application Number:
20120213252
A controller for advanced receivers configures a plurality of advanced receiver modules based on figures of merit computed on the input signal. The controller also selects the appropriate output signal based on figures of merit of either the input or the output signals. The controller decisions can also be made in a bursty manner, where only a subset of the decisions to be made are made at a given time, thereby limiting the processing load of the control processor.
Multiple Word Data Bus Inversion
Granted: August 16, 2012
Application Number:
20120206280
A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of…
High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization
Granted: August 16, 2012
Application Number:
20120207196
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
INTERFACE CLOCK MANAGEMENT
Granted: August 16, 2012
Application Number:
20120210157
The timing of the synchronous interface is controlled by a dock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller…
LINEAR EQUALIZER WITH PASSIVE NETWORK AND EMBEDDED LEVEL SHIFTER
Granted: August 9, 2012
Application Number:
20120200375
The disclosed embodiments relate to the design of a linear equalizer that supports low-power, high-speed data transfers. In some embodiments, this linear equalizer contains a passive network that provides selective frequency peaking in a frequency range associated with a falling edge of a frequency response of the channel. It also includes a level shifter coupled between the channel and the passive network, wherein the level shifter is an active component that provides amplification…
INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRST CODE, A STROBE SIGNAL AFTER A DELAY AND DATA TO A DYNAMIC RANDOM ACCESS MEMORY (DRAM)
Granted: August 9, 2012
Application Number:
20120201089
An integrated circuit device comprises an interface to transmit a first code, a strobe signal after a delay and data to a dynamic random access memory (DRAM). The first code indicates that data is to be written to the DRAM. The first code is registered by the DRAM on one or more edges of an external clock signal received by the DRAM. The strobe signal specifies one or more discrete points in time synchronous with the external clock signal at which the data is registered by the DRAM.
CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM
Granted: August 9, 2012
Application Number:
20120204012
A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor…
Methods for managing alignment and latency in interference suppression
Granted: August 2, 2012
Application Number:
20120195360
An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. Various techniques may be…
Signal Distribution Networks and Related Methods
Granted: July 26, 2012
Application Number:
20120187988
A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal…
DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATION
Granted: July 26, 2012
Application Number:
20120191943
A dynamic serialized command and address (CA) protocol with cycle-accurate matching between the PHY interface and the DFI interface is described. This CA protocol facilitates the use of a common memory-controller control logic with different CA bus configurations. With this CA protocol, CA packets for different memory operations have different formats. The size and the position of the CA packets vary relative to boundaries of DFI clock cycles, and the CA packets can extend beyond DFI…
Methods and Circuits for Calibrating Multi-Modal Termination Schemes
Granted: July 26, 2012
Application Number:
20120187978
Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different…
Methods and Systems for Reducing Supply and Termination Noise
Granted: July 19, 2012
Application Number:
20120182044
Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.
Scalable Unified Memory Architecture
Granted: July 19, 2012
Application Number:
20120182304
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides…
MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION
Granted: July 19, 2012
Application Number:
20120182821
A memory system that includes a memory device and a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row in a second storage region of the memory bank. The memory request includes a first row address identifying the first row and a second row address identifying the second row. Next, the memory device routes the first…
Methods and Systems for Enhancing Wireless Coverage
Granted: July 19, 2012
Application Number:
20120184242
Described are methods, devices, and systems to provide enhanced wireless coverage for wireless mobile stations by facilitating centralized authentication for a variety of unrelated networks. The mobile stations can then access Internet and telephony resources via the various networks for improved coverage and bandwidth. Some embodiments support the extension of network coverage using wireless-access points that can be partitioned into multiple virtual access points, one associated with…
FAST POWER-ON BIAS CIRCUIT
Granted: July 5, 2012
Application Number:
20120169412
Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.
Semiconductor Memory Device with Hierarchical Bitlines
Granted: July 5, 2012
Application Number:
20120170356
A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower…
MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE
Granted: July 5, 2012
Application Number:
20120170399
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells…
Methods And Apparatus For Synchronizing Communication With A Memory Controller
Granted: June 28, 2012
Application Number:
20120166863
A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
