REDUCING CROSSTALK BETWEEN MULTIPLE INTERCONNECTS
Granted: December 6, 2012
Application Number:
20120306568
Embodiments reduce crosstalk between multiple interconnects in a printed circuit board environment. Further, embodiments perform frequency-dependent modal decomposition of characteristics of two or more interconnects spanning one or more integrated circuits on an interconnect substrate. In addition, each interconnect includes one or more cascaded coupled traces, where the cascaded coupled traces have one or more discontinuities in a heterogeneous medium.
Phase Detection Circuits and Methods
Granted: December 6, 2012
Application Number:
20120306538
A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit…
Driver Calibration Methods and Circuits
Granted: November 29, 2012
Application Number:
20120299619
Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.
LIGHT COLLECTING AND EMITTING APPARATUS, METHOD, AND APPLICATIONS
Granted: November 22, 2012
Application Number:
20120294578
A light guide apparatus includes a light guide layer having a top surface and a bottom surface, and a transversely oriented side-end surface that forms an output aperture of the light guide, characterized by an index of refraction, n1, and further characterized by a length dimension in an intended light propagation direction towards the output aperture, where the intended light propagation direction is a z-axis direction of a Cartesian coordinate system; and a plurality of light…
LIGHTING ASSEMBLY
Granted: November 15, 2012
Application Number:
20120287668
A lighting assembly includes a light guide and a light source. The light guide has opposed major surfaces and side surfaces extending between the major surfaces. The light source is at an apex region between two side surfaces and is configured to input light to the light guide. The side surfaces comprise a stepped reflective side surface extending from the apex region and comprising a first reflective step and a second reflective step, and an output side surface extending from the apex…
LIGHTING ASSEMBLY
Granted: November 15, 2012
Application Number:
20120287671
A lighting assembly includes a light engine and a light guide. The light engine edge lights the light guide and includes a control assembly that controls light output according to one or more parameters to produce light output from the lighting assembly with a desired characteristic. Lighting assemblies are combined to form a modular lighting assembly.
LIGHTING ASSEMBLY
Granted: November 8, 2012
Application Number:
20120281432
A lighting assembly includes a light guide having opposed major surfaces between which light propagates by total internal reflection and a light input edge. The light assembly also includes a light engine. The light engine has a heat conductive armature having a receptacle for a portion of the light guide that includes the light input edge and a light source retained by and thermally coupled to the armature. The armature functions as a heat sink for dissipating heat generated by the…
Low Power Memory Device
Granted: November 8, 2012
Application Number:
20120281489
“A method of operation within a memory device comprises receiving address information and corresponding enable information. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first…
ADAPTIVELY TIME-MULTIPLEXING MEMORY REFERENCES FROM MULTIPLE PROCESSOR CORES
Granted: November 1, 2012
Application Number:
20120278583
The disclosed embodiments relate to a system for processing memory references received from multiple processor cores. During operation, the system monitors the memory references to determine whether memory references from different processor cores are interfering with each other as the memory references are processed by a memory system. If memory references from different processor cores are interfering with each other, the system time-multiplexes the processing of memory references…
LIGHTING ASSEMBLY
Granted: October 25, 2012
Application Number:
20120268966
A lighting assembly includes a light guide having a first major surface, a second major surface opposite the first major surface, a light input edge, and an end edge distal the light input edge. Light input to the light guide through the light input edge propagates by total internal reflection toward the end edge. The lighting assembly further includes light extracting elements at least one of the major surfaces of the light guide, the light extracting elements configured to extract…
CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM
Granted: October 18, 2012
Application Number:
20120262998
Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.
PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE
Granted: September 27, 2012
Application Number:
20120243632
Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
Staggered Mode Transitions in a Segmented Interface
Granted: September 20, 2012
Application Number:
20120236659
A memory integrated circuit comprises first and second memory arrays and first and second interfaces. The first interface receives a signal for accessing a memory location in one of the first and the second memory arrays during a first time interval. The second interface receives a signal for accessing a memory location in one of the first and the second memory arrays during the first time interval. The first interface receives signals for accessing memory locations in the first and the…
PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING
Granted: September 20, 2012
Application Number:
20120236917
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first…
DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE
Granted: September 13, 2012
Application Number:
20120230134
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense…
INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR
Granted: September 6, 2012
Application Number:
20120224407
Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use…
Techniques for Phase Detection
Granted: August 30, 2012
Application Number:
20120218001
A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of…
RECONFIGURABLE MEMORY CONTROLLER
Granted: August 30, 2012
Application Number:
20120221769
Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in…
BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION
Granted: August 30, 2012
Application Number:
20120221902
The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty…
METHOD OF OPERATION OF A MEMORY DEVICE AND SYSTEM INCLUDING INITIALIZATION AT A FIRST FREQUENCY AND OPERATION AT A SECOND FREQUENCEY AND A POWER DOWN EXIT MODE
Granted: August 23, 2012
Application Number:
20120216059
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first…
