DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM
Granted: May 19, 2011
Application Number:
20110119425
The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of…
REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT
Granted: May 5, 2011
Application Number:
20110102043
A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock…
Systems and Methods for Parallel Signal Cancellation
Granted: April 28, 2011
Application Number:
20110096767
A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the…
FREQUENCY RESPONSIVE BUS CODING
Granted: April 14, 2011
Application Number:
20110084737
A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a…
Interference Suppression for CDMA Systems
Granted: April 7, 2011
Application Number:
20110080923
Interference is cancelled from a baseband signal by synthesizing interference from estimated symbols in interfering subchannels. The estimated symbols are hard-coded, soft weighted, or zeroed, depending on the value of an estimated pre-processed signal-to-interference-and-noise ratio (SINR) in each subchannel in order to maximize a postprocessed SINR. The estimated pre-processed SINR is obtained from averages of estimated symbol energies and estimated noise variances, or from related…
Method and Apparatus for Interference Suppression with Efficient Matrix Inversion in a DS-CDMA System
Granted: March 24, 2011
Application Number:
20110069742
A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
Capacitive-coupled Crosstalk Cancellation
Granted: March 24, 2011
Application Number:
20110069782
This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest…
Advanced Signal Processors for Interference Suppression in Baseband Receivers
Granted: March 24, 2011
Application Number:
20110069796
A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the…
Segmentation Of Flash Memory For Partial Volatile Storage
Granted: March 17, 2011
Application Number:
20110066792
This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile…
Systems and Methods for Serial Cancellation
Granted: March 17, 2011
Application Number:
20110064172
A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
Methods for Estimation and Interference Cancellation for signal processing
Granted: March 17, 2011
Application Number:
20110064066
A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES
Granted: March 10, 2011
Application Number:
20110060868
This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks (302), each including nonvolatile memory cells. The nonvolatile memory further includes at least one sharable resource (306), such as a power supply module, a program controller or an erase controller, wherein each sharable resource (306) is assignable to at least two of the concurrently accessible memory banks to enable a first type of memory operation. The…
ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION
Granted: March 3, 2011
Application Number:
20110051854
Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may…
METHOD AND APPARATUS FOR POWER SEQUENCE TIMING TO MITIGATE SUPPLY RESONANCE IN POWER DISTRIBUTION NETWORK
Granted: February 24, 2011
Application Number:
20110043220
The transient load current of a circuit powered by a power distribution network is increased in a plurality of steps, with the step transition times being adjusted based on the transient noise of the power distribution network. This reduces the resonance noise that would otherwise occur in the supply current of the power distribution network.
Iterative Interference Canceler for Wireless Multiple-Access Systems with Multiple Receive Antennas
Granted: February 24, 2011
Application Number:
20110044378
This invention teaches to the details of an interference canceling receiver for canceling intra-cell and inter-cell interference in coded, multiple-access, spread spectrum transmissions that propagate through frequency selective communication channels to a multiplicity of receive antennas. The receiver is designed or adapted through the repeated use of symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimates. Receiver…
Scalable Unified Memory Architecture
Granted: February 17, 2011
Application Number:
20110037772
A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides…
ENCODING DATA WITH MINIMUM HAMMING WEIGHT VARIATION
Granted: February 3, 2011
Application Number:
20110025533
M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2m) of data patterns in the m-bit data but that the n-bit data has Hamming Weights (HWs) with minimum (smallest possible) variation. Specifically, encoder logic is configured to receive 2m of m-bit data patterns and encode the 2m of m-bit data patterns to n-bit encoded data patterns, n being greater than m and me being a positive integer…
Method and System for Balancing Receive-Side Supply Load
Granted: February 3, 2011
Application Number:
20110029801
Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between…
Partial Response Receiver And Related Method
Granted: January 27, 2011
Application Number:
20110018599
A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects…
Advanced signal processors for Interference Cancellation in baseband receivers
Granted: January 27, 2011
Application Number:
20110019656
An interference canceller comprises a composite interference vector (CIV) generator configured to produce a CIV by combining soft and/or hard estimates of interference, an interference-cancelling operator configured for generating a soft projection operator, and a soft-projection canceller configured for performing a soft projection of the received baseband signal to output an interference-cancelled signal. Weights used in the soft-projection operator are selected to maximize a…
