Methods and Systems for Reducing Supply and Termination Noise
Granted: January 27, 2011
Application Number:
20110019760
A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply voltages limits the maximum supply current used to express the signals and to transition between adjacent symbol sets. Limiting supply current ameliorates problems associated with simultaneous switching noise (SSN). At…
PROGRAMMABLE MEMORY REPAIR SCHEME
Granted: January 20, 2011
Application Number:
20110016352
The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate…
APPARATUS AND METHOD FOR REDUCING PIXEL OPERATIONAL VOLTAGE IN MEMS-BASED OPTICAL DISPLAYS
Granted: January 13, 2011
Application Number:
20110007377
Embodiments of a display comprising pixels formed from suitably tethered deformable membrane-based MEMS subsystems are provided that include the means to dynamically alter the in-plane tension, and thus the effective spring constant, of the deformable membrane being ponderomotively propelled between active and inactive optical states, said dynamic alteration being effected by exploiting transverse piezoelectric properties of the deformable membranes. Manipulating the spring constant can…
PIECEWISE ERASURE OF FLASH MEMORY
Granted: January 6, 2011
Application Number:
20110004726
Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase…
Advanced Signal Processors for Interference Cancellation in Baseband Receivers
Granted: December 30, 2010
Application Number:
20100329402
A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the…
METHOD AND APPARATUS FOR SELECTIVELY APPLYING INTERFERENCE CANCELLATION IN SPREAD SPECTRUM SYSTEMS
Granted: December 23, 2010
Application Number:
20100323624
The present invention is directed to the selective provision of interference canceled signal streams to demodulating fingers in a communication receiver. According to the present invention, potential interferer signal paths are identified. Signal streams having one or more potential interferer signals removed or canceled are created, and a correlation is performed to determine whether the strength of a desired signal path increased as a result. If the correlation indicates that the…
Driver Calibration Methods and Circuits
Granted: December 16, 2010
Application Number:
20100318311
Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.
HIGH-SPEED SOURCE-SYNCHRONOUS SIGNALING
Granted: December 16, 2010
Application Number:
20100315142
A system for communicating data between a first integrated circuit device and a second integrated circuit device. The first iterated circuit device transmits a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition. The first integrated circuit device then delays the data, so that the data is delayed relative to the timing signal by a first predetermined delay time. Next, the first integrated circuit device…
ASYMMETRIC COMMUNICATION ON SHARED LINKS
Granted: December 9, 2010
Application Number:
20100309964
Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword,…
EDGE-BASED LOSS-OF-SIGNAL DETECTION
Granted: December 9, 2010
Application Number:
20100309791
Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
SIMPLE MATRIX ADDRESSING IN A DISPLAY
Granted: December 2, 2010
Application Number:
20100302229
An addressing mechanism for charging and discharging quasi-capacitive elements in an X-Y matrix. The addressing mechanism may be configured to toggle a resistor-capacitor (RC) time constant between large and small values such as by opening or closing a circuit path to a low impedance resistor disposed in parallel with a higher impedance in-line resistor. When this occurs, elements in the X-Y matrix can be addressed and controlled. The X-Y matrix may be comprised of multiple “rows”…
METHOD AND APPARATUS FOR DETERMINING A CALIBRATION SIGNAL
Granted: November 25, 2010
Application Number:
20100296566
Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the…
Receiver With Enhanced Clock And Data Recovery
Granted: November 18, 2010
Application Number:
20100289544
A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received…
ENCODING AND DECODING TECHNIQUES WITH IMPROVED TIMING MARGIN
Granted: November 18, 2010
Application Number:
20100290481
Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of…
ENCODING AND DECODING TECHNIQUES FOR BANDWIDTH-EFFICIENT COMMUNICATION
Granted: October 21, 2010
Application Number:
20100265109
An encoder encodes data into parallel codewords. Each codeword is expressed as a set of logic 0s and a set of logic 1s on two sets of output nodes. The encoder selects a current codeword which differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. The current codeword is selected such that the first and second sets of nodes are different than…
Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance
Granted: October 14, 2010
Application Number:
20100259295
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination…
TECHNIQUE FOR DETERMINING AN ANGLE OF ARRIVAL IN A COMMUNICATION SYSTEM
Granted: October 14, 2010
Application Number:
20100259449
Embodiments of a circuit are described. In this circuit, a transmit circuit provides signals to antenna elements during an acquisition mode, where a given signal to a given antenna element includes at least two frequency components having associated phases, and where the phase of a given frequency component in the given signal is different from phases of the given frequency component for the other antenna elements. Moreover, an output node couples the transmit circuit to the antenna…
Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes
Granted: October 14, 2010
Application Number:
20100262790
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The…
METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
Granted: September 30, 2010
Application Number:
20100251040
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.…
Configurable On-Die Termination
Granted: September 23, 2010
Application Number:
20100237903
Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
