Dual loop clock recovery circuit
Granted: October 15, 2009
Application Number:
20090257542
A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The…
Selectable-Tap Equalizer
Granted: October 8, 2009
Application Number:
20090252213
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of…
Embedded Source-Synchronous Clock Signals
Granted: October 1, 2009
Application Number:
20090243681
A synchronous communication system includes two transmitters that transmit respective first and second data signals that are phase offset from one another by about 90 degrees. On the receive side, a pair of extraction circuits extract a first clock signal from the first data signal and a second clock signal from the second data signal. The clock signals are offset from one another by about 90 degrees due to the phase offset of the corresponding data signals. Edges of the first clock…
TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC DEVICES AND SYSTEMS
Granted: September 24, 2009
Application Number:
20090240448
A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to…
POWER SUPPLY NOISE REJECTION IN PLL OR DLL CIRCUITS
Granted: September 17, 2009
Application Number:
20090231002
A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock.
MEMORY ERROR DETECTION
Granted: September 17, 2009
Application Number:
20090235113
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a…
Locked Loop Circuit With Clock Hold Function
Granted: September 3, 2009
Application Number:
20090219067
A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch…
RENDERING DYNAMIC OBJECTS USING GEOMETRY LEVEL-OF-DETAIL IN A GRAPHICS PROCESSING UNIT
Granted: August 6, 2009
Application Number:
20090195541
The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through…
Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
Granted: August 6, 2009
Application Number:
20090198924
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address…
TECHNIQUE FOR LOW-POWER OPERATION OF A WIRELESS DEVICE
Granted: July 23, 2009
Application Number:
20090186584
Embodiments of a circuit are described. In this circuit, a receiver includes at least one input node that receives one or more signals from one or more antenna elements. Note that a given signal from a given antenna element may have an associated fixed bandwidth and/or may include directional information corresponding to a region in a space. Moreover, the receiver includes a measurement circuit, coupled to at least the one input node, that determines whether a metric of the given signal…
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
Granted: June 25, 2009
Application Number:
20090161453
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or…
TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM
Granted: June 25, 2009
Application Number:
20090164677
This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific…
PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE
Granted: May 21, 2009
Application Number:
20090129505
Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter.
COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK
Granted: May 21, 2009
Application Number:
20090132741
A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component…
FILE ACCESSING AND RETRIEVAL USING SOFT DIGITAL RIGHTS MANAGEMENT TECHNOLOGY
Granted: May 14, 2009
Application Number:
20090126027
The subject matter disclosed herein relates to a method and/or system for enabling access to computer file content using an open routine having a proprietary argument.
METHOD AND APPARATUS FOR DATA RECOVERY
Granted: April 30, 2009
Application Number:
20090110115
A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data recovery from corresponding sample sets. One function applied for the determination, includes taking a first mean transition position in a first group of sample sets, taking a second mean transition position in…
Crosstalk Minimization in Serial Link Systems
Granted: April 23, 2009
Application Number:
20090103572
Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring…
SYSTEM FOR PHASE OFFSET CANCELLATION IN SYSTEMS USING MULTI-PHASE CLOCKS
Granted: April 16, 2009
Application Number:
20090097605
A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system comprises at least two phase detectors coupled to the multi-phase clock generator for receiving component clock signals of the multi-phase clock generator, wherein at least some of the component clock signals are offset from each…
UTILIZING MASKED DATA BITS DURING ACCESSES TO A MEMORY
Granted: April 2, 2009
Application Number:
20090089557
Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of…
Equalizing Transceiver With Reduced Parasitic Capacitance
Granted: March 12, 2009
Application Number:
20090066376
A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select…
