Margin Test Methods And Circuits
Granted: March 25, 2010
Application Number:
20100074314
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device…
Memory System Supporting Nonvolatile Physical Memory
Granted: March 25, 2010
Application Number:
20100077136
A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
Memory System with Point-to-Point Request Interconnect
Granted: March 25, 2010
Application Number:
20100077267
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The…
High-Speed Low-Power Differential Receiver
Granted: March 18, 2010
Application Number:
20100066450
A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential…
Memory Systems And Methods For Dynamically Phase Adjusting A Write Strobe And Data To Account For Receive-Clock Drift
Granted: March 18, 2010
Application Number:
20100067314
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses…
Adaptive Receive-Side Equalization
Granted: March 4, 2010
Application Number:
20100054323
An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data…
DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
Granted: March 4, 2010
Application Number:
20100058100
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring…
Data-Width Translation Between Variable-Width and Fixed-Width Data Ports
Granted: February 25, 2010
Application Number:
20100050010
Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical…
Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices
Granted: February 25, 2010
Application Number:
20100046600
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the…
Adaptive Receive-Side Equalization
Granted: February 25, 2010
Application Number:
20100046597
An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data…
CODING METHODS AND SYSTEMS FOR IMPROVED ERROR MARGINS
Granted: February 18, 2010
Application Number:
20100040169
Each symbol in a sequence of codewords is expressed as a voltage level representative of a one or zero, and each codeword includes both levels. Sense amplifiers at the receiver compare all pairs of symbols in each codeword. Comparisons based upon like symbol values provide mid-range sensed voltages, and comparisons based upon disparate symbols values provide relatively higher or lower sensed voltages. Sampling the high and low voltages produces determinate sample values, whereas sampling…
MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA
Granted: February 4, 2010
Application Number:
20100030955
An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from…
EQUALIZING TRANSMITTER AND METHOD OF OPERATION
Granted: February 4, 2010
Application Number:
20100027712
A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.
DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing
Granted: January 28, 2010
Application Number:
20100020861
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.
High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization
Granted: January 14, 2010
Application Number:
20100008414
A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
BIMODAL MEMORY CONTROLLER
Granted: December 31, 2009
Application Number:
20090327565
A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O…
Method And Apparatus For Test And Characterization Of Semiconductor Components
Granted: December 31, 2009
Application Number:
20090322370
A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with…
System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices
Granted: December 24, 2009
Application Number:
20090319719
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the…
SELECTIVE SWITCHING OF A MEMORY BUS
Granted: December 3, 2009
Application Number:
20090300260
In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus…
Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance
Granted: November 12, 2009
Application Number:
20090278565
Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination…
