System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices
Granted: May 8, 2008
Application Number:
20080109596
A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the…
MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE
Granted: April 3, 2008
Application Number:
20080080261
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address…
Power supply noise rejection in PLL or DLL circuits
Granted: March 20, 2008
Application Number:
20080068056
A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock.
Selectable-Tap Equalizer
Granted: February 28, 2008
Application Number:
20080049822
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of…
Integrated Circuit Device and Signaling Method with Topographic Dependent Equalization Coefficient
Granted: February 28, 2008
Application Number:
20080052434
An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device. The value is representative of an equalization co-efficient setting that compensates for signals present on an external signal line. The signals present on the external signal line comprise one…
Method of Controlling A Memory Device Having a Memory Core
Granted: February 21, 2008
Application Number:
20080043546
Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write…
Buffered Memory Having A Control Bus And Dedicated Data Lines
Granted: February 7, 2008
Application Number:
20080034130
A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in…
COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
Granted: December 6, 2007
Application Number:
20070280393
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING
Granted: October 4, 2007
Application Number:
20070230549
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameters and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first…
WAVE SHAPING OUTPUT DRIVER TO ADJUST SLEW RATE AND/OR PRE-EMPHASIS OF AN OUTPUT SIGNAL
Granted: September 6, 2007
Application Number:
20070205811
Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the…
REGULATED ADAPTIVE-BANDWIDTH PLL/DLL USING SELF-BIASING CURRENT FROM A VCO/VCDL
Granted: August 30, 2007
Application Number:
20070200603
A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the voltage regulator. In an embodiment of the present invention, a component of the PLL/DLL includes a bias-generating device, such as a MOSFET p-type transistor having a drain coupled to the interconnect.…
DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
Granted: August 30, 2007
Application Number:
20070204184
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring…
MEMORY DEVICE
Granted: August 30, 2007
Application Number:
20070201280
A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals…
Processor controlled interface
Granted: July 26, 2007
Application Number:
20070174586
Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.
METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
Granted: July 19, 2007
Application Number:
20070165472
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.…
TRANSCEIVER WITH SELECTABLE DATA RATE
Granted: June 28, 2007
Application Number:
20070147569
An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the…
MEMORY CONTROLLER AND METHOD FOR OPERATING A MEMORY CONTROLLER HAVING AN INTEGRATED BIT ERROR RATE CIRCUIT
Granted: June 14, 2007
Application Number:
20070136623
A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory…
Multiple Channel Modules and Bus Systems Using Same
Granted: May 31, 2007
Application Number:
20070120575
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
PHASE SYNCHRONIZATION FOR WIDE AREA INTEGRATED CIRCUITS
Granted: May 31, 2007
Application Number:
20070124636
A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a…
CURRENT CONTROL TECHNIQUE
Granted: May 24, 2007
Application Number:
20070115043
An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
