TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
Granted: May 24, 2007
Application Number:
20070118711
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
Drift Tracking Feedback for Communication Channels
Granted: April 19, 2007
Application Number:
20070088968
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring…
SYSTEM INCLUDING A BUFFERED MEMORY MODULE
Granted: April 19, 2007
Application Number:
20070088995
According to embodiments, a system includes a master device and a first memory module having a plurality of integrated circuit memory devices and a plurality of integrated circuit buffer devices that operate in first and second modes of operation (bypass mode). In a first mode of operation, a first memory module provides read data from the plurality of integrated circuit memory devices (via a integrated circuit buffer device) on a first signal path to the master and a second memory…
METHOD AND APPARATUS FOR ADJUSTING THE PERFORMANCE OF A SYNCHRONOUS MEMORY SYSTEM
Granted: April 12, 2007
Application Number:
20070083700
A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
MEMORY SYSTEM AND DEVICE WITH SERIALIZED DATA TRANSFER
Granted: March 29, 2007
Application Number:
20070073926
A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
Method And Apparatus For Evaluating And Optimizing A Signaling System
Granted: March 22, 2007
Application Number:
20070064510
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.…
Power supply shunt
Granted: March 15, 2007
Application Number:
20070058306
A power supply shunt for an electronic circuit. The power supply shunt includes at least two Field Effect Transistors (FETs), a first of the FETs having its drain coupled to a terminal of an electronic circuit and its source coupled to another of the FETs, and a second of the FETs having its source coupled to ground and its drain coupled to another of the FETs. The first FET has a bulk terminal that floats with respect to ground.
Low jitter clock recovery circuit
Granted: March 15, 2007
Application Number:
20070058768
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a…
TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
Granted: January 11, 2007
Application Number:
20070011426
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
PVT drift compensation
Granted: December 28, 2006
Application Number:
20060294410
A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on the comparison; and a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the…
COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
Granted: December 28, 2006
Application Number:
20060291574
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
Self-powered devices and methods
Granted: November 30, 2006
Application Number:
20060271678
A system includes a computing device that selectively communicates with a self-powered device. The self-powered device has several modes of operation, including a first low-power mode of operation and a second high-power mode of operation. The self-powered device is to communicate with the computing device when the self-powered device is in the second mode of operation. The self-powered device may conserve power by alternating between the first mode of operation and the second mode of…
FAULT-TOLERANT CLOCK GENERATOR
Granted: November 9, 2006
Application Number:
20060250160
A fault-tolerant clock generation circuit. First and second clock signal generators are provided to generate first and second clock signals. The second clock signal generator includes a locked loop circuit that, in a first operating mode, adjusts the phase of the second clock signal as necessary to maintain phase alignment between the first and second clock signals. A fail detect circuit is provided to determine whether a failure relating to generation of the first clock signal has…
Technique for testing interconnections between electronic components
Granted: November 2, 2006
Application Number:
20060247886
A technique for testing interconnections between electronic components is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for testing interconnections between electronic components. The method may comprise sending a command from a test controller to a plurality of electronic components via a first communication path, wherein the command comprises an instruction for one or more of the plurality of electronic components to transmit a…
METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM
Granted: October 19, 2006
Application Number:
20060236183
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns.…
Low power, DC-balanced serial link transmitter
Granted: July 27, 2006
Application Number:
20060164264
A transmitter for a data communication system that comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second…
Communication system with low power, DC-balanced serial link
Granted: July 27, 2006
Application Number:
20060165185
A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates…
High Speed Communication System With A Feedback Synchronization Loop
Granted: July 27, 2006
Application Number:
20060165186
In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing…
A LOW POWER, DC-BALANCED SERIAL LINK
Granted: July 27, 2006
Application Number:
20060165195
A receiver for a data communication system which comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated…
Periodic interface calibration for high speed communication
Granted: July 20, 2006
Application Number:
20060159113
A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with…
