Memory system with channel multiplexing of multiple memory devices
Granted: April 29, 2004
Application Number:
20040081005
A high-speed memory system is disclosed in which a single command effects control over either a single memory device or a plurality of memory devices depending on a present mode of operation. Such control may effect data transfer between the one or more memory devices and a memory controller, as well as operating state transitions or power mode transitions for the memory devices. Similarly, various configurations of relatively low bandwidth memory devices respond as a selectively…
Method and apparatus for digital duty cycle adjustment
Granted: April 22, 2004
Application Number:
20040075462
Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.
Calibrated data communication system and method
Granted: April 22, 2004
Application Number:
20040076192
A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device…
Dram core refresh with reduced spike current
Granted: April 1, 2004
Application Number:
20040062120
A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be…
Method and apparatus for signaling between devices of a memory system
Granted: March 18, 2004
Application Number:
20040054845
A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals…
Apparatus and method for a digital delay locked loop
Granted: March 11, 2004
Application Number:
20040046597
A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a received clock signal. An output tap from one delay line is used to produce a rising edge in an output clock signal while a corresponding tap in the complementary delay line is used to produce a falling edge in the output signal…
METHOD AND APPARATUS FOR SELECTABLY PROVIDING SINGLE-ENDED AND DIFFERENTIAL SIGNALING WITH CONTROLLABLE IMPEDANCE AND TRANSITION TIME
Granted: January 1, 2004
Application Number:
20040000924
A method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time is provided. According to the method and apparatus, a differential signal can be transmitted over two wires or two single-ended signals can be transmitted over the two wires. According to the method and apparatus, termination may be selected among a single-reference termination, a center termination, or a high-impedance termination. Regardless of the…
Semiconductor package with a controlled impedance bus and method of forming same
Granted: October 30, 2003
Application Number:
20030202373
An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.
Pipelined memory controller and method of controlling access to memory devices in a memory system
Granted: October 16, 2003
Application Number:
20030196059
A memory controller for a high-performance memory system has a pipeline architecture for generating control commands which satisfy logical, timing, and physical constraints imposed on control commands by the memory system. The pipelined memory controller includes a bank state cache lookup for determining a memory bank state for a target memory bank to which a control command is addressed, and a hazard detector for determining when a memory bank does not have a proper memory bank state…
Memory controller with power management logic
Granted: August 21, 2003
Application Number:
20030159004
A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache…
Apparatus for data recovery in a synchronous chip-to-chip system
Granted: June 19, 2003
Application Number:
20030112909
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform…
Active impedance compensation
Granted: June 12, 2003
Application Number:
20030110454
Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.
Method and apparatus for fail-safe resynchronization with minimum latency
Granted: March 20, 2003
Application Number:
20030053489
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system…
Multiple channel modules and bus systems using same
Granted: January 9, 2003
Application Number:
20030007337
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
Apparatus for data recovery in a synchronous chip-to-chip system
Granted: December 26, 2002
Application Number:
20020196883
An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform…
High performance cost optimized memory
Granted: November 28, 2002
Application Number:
20020178324
A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.
Apparatus and method for maximizing information transfers over limited interconnect resources
Granted: October 24, 2002
Application Number:
20020156985
The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address…
Apparatus and method for generating a distributed clock signal using gear ratio techniques
Granted: October 17, 2002
Application Number:
20020150189
The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are…
Redistributed bond pads in stacked integrated circuit die package
Granted: September 12, 2002
Application Number:
20020127775
A semiconductor module having a first integrated circuit die having a planar surface. The first integrated circuit die has a first conductive pad disposed substantially on the planar surface and a redistributed conductive pad electrically connected to the first conductive pad. The redistributed conductive pad is disposed near a periphery of the planar surface. The semiconductor module has a second integrated circuit die stacked adjacent to the planar surface and offset from the…
Chip socket assembly and chip file assembly for semiconductor chips
Granted: May 9, 2002
Application Number:
20020055285
A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace…
