Apparatus and method for topography dependent signaling
Granted: May 9, 2002
Application Number:
20020056016
Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography…
Charge compensation control circuit and method for use with output driver
Granted: April 18, 2002
Application Number:
20020043997
An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in various ways to generate the q-node signal. The output current driver is responsive to current control bits to select a amount of output drive current. In addition, the output multiplexor is…
Method and apparatus for reducing worst case power
Granted: March 7, 2002
Application Number:
20020027447
An apparatus for reducing worst-case power consumption. The apparatus includes a first signal that has signal transitions. A circuit path is provided for transmitting a second signal through buffered circuit sections. Logic circuitry is coupled to the circuit path and to the first signal. The logic circuitry uses the first signal to reduce a sum of signal transitions of the second signal as the second signal propagates from one buffered section of the circuit path to another buffered…
Apparatus and method for edge based duty cycle conversion
Granted: February 14, 2002
Application Number:
20020017936
A duty cycle converter generating a pair of output signals whose cross-point duty cycle is substantially equal to the edge duty cycle of a pair of input signals. The duty cycle converter includes an edge detector and a signal generator. The edge detector detects and indicates a first transition of a first input signal and a second transition of a second input signal. The signal generator takes the outputs of the edge detector and generates a first output signal and a second output…
Chip socket assembly and chip file assembly for semiconductor chips
Granted: February 7, 2002
Application Number:
20020016091
A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace…
Multiple channel modules and bus systems using same
Granted: December 20, 2001
Application Number:
20010053069
Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
Power control system for synchronous memory device
Granted: November 29, 2001
Application Number:
20010047493
A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the memory access to make the power control transparent to the user accessing the memory core. The memory device can dynamically switch between a fast and a slow clock depending upon the needed…
Output driver circuit with well-controlled output impedance
Granted: November 1, 2001
Application Number:
20010035768
An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.
