MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS
Granted: July 17, 2014
Application Number:
20140201553
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second…
COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS
Granted: July 10, 2014
Application Number:
20140192940
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
Memory Error Detection
Granted: July 3, 2014
Application Number:
20140189466
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a…
DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
Granted: July 3, 2014
Application Number:
20140185725
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring…
SYSTEM AND METHOD FOR PERFORMING MEMORY OPERATIONS ON RRAM CELLS
Granted: July 3, 2014
Application Number:
20140185362
A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory…
Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock Drift
Granted: June 26, 2014
Application Number:
20140181393
A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller…
Reconfigurable Memory Controller
Granted: June 26, 2014
Application Number:
20140181331
Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in…
Pixel Structure and Reset Scheme
Granted: June 26, 2014
Application Number:
20140175264
An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable.
Methods and Circuits for Securing Proprietary Memory Transactions
Granted: June 19, 2014
Application Number:
20140173238
Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The…
MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
Granted: June 19, 2014
Application Number:
20140173240
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing
Granted: June 19, 2014
Application Number:
20140169438
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the…
Memory Disturbance Recovery Mechanism
Granted: June 12, 2014
Application Number:
20140164823
Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The…
Margin Test Methods and Circuits
Granted: June 12, 2014
Application Number:
20140161166
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device…
High Fill-Factor Image Sensor Architecture
Granted: June 12, 2014
Application Number:
20140158863
An image sensor architecture is implemented within an image sensor system. Image sensor pixels include pixel regions, and each pixel region includes a photosensor, a reset circuit, and a readout circuit. The readout circuit receives enable signals from an enable signal line, and outputs a pixel signal representative of light captured by the photosensor on a combination input/output line. The reset circuit resets the photosensor in response to receiving a first reset signal on a reset…
CONTENT ADDRESSABLE MEMORY
Granted: June 5, 2014
Application Number:
20140153310
A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on…
Lighting Assembly with Defined Angular Output
Granted: June 5, 2014
Application Number:
20140153285
A lighting assembly includes a light guide and solid-state light emitters to edge-light the light guide, the light emitters arrayed along a transverse direction. The light guide includes two or more sets of optical elements of well-defined shape. Light output from the lighting assembly by the first and second set of optical elements have a first and a second light ray angle distribution, respectively. The optical elements are configured such that when measured in a plane perpendicular to…
LIGHTING ASSEMBLY WITH A LIGHT GUIDE HAVING LIGHT-REDIRECTING EDGE FEATURES
Granted: June 5, 2014
Application Number:
20140153282
A lighting assembly includes a light source to emit on-axis light rays at smaller angles relative to an optical axis of the light source, and off-axis light rays at larger angles relative to the optical axis and spectrally different from the on-axis light rays. The lighting assembly additionally includes a light guide having a light input edge adjacent the light source and opposed major surfaces between which light from the light source propagates by total internal reflection. The light…
METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER
Granted: June 5, 2014
Application Number:
20140152357
A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
High-Speed Low Power Stacked Transceiver
Granted: May 29, 2014
Application Number:
20140145760
A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.
CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING
Granted: May 29, 2014
Application Number:
20140149618
A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while…
