CALIBRATION PROTOCOL FOR COMMAND AND ADDRESS BUS VOLTAGE REFERENCE IN LOW-SWING SINGLE-ENDED SIGNALING
Granted: May 29, 2014
Application Number:
20140149618
A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while…
Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection
Granted: May 22, 2014
Application Number:
20140140419
A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
RECEIVER WITH DUOBINARY MODE OF OPERATION
Granted: May 22, 2014
Application Number:
20140140389
An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder.…
Strobe Acquisition and Tracking
Granted: May 22, 2014
Application Number:
20140140149
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in…
INTEGRATED CIRCUIT WITH CONFIGURABLE ON-DIE TERMINATION
Granted: May 22, 2014
Application Number:
20140139261
Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.
Periodic Calibration For Communication Channels By Drift Tracking
Granted: May 15, 2014
Application Number:
20140133536
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first…
MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION
Granted: May 15, 2014
Application Number:
20140133259
The disclosed embodiments relate to components of a memory system that support error detection and correction by means of storage and retrieval of error correcting codes. In specific embodiments, this memory system includes a memory device, which further contains a memory bank. During operation, the memory device receives a request to concurrently access a data word at a first row in a first storage region of the memory bank and error information associated with the data at a second row…
On-Die Termination of Address and Command Signals
Granted: April 24, 2014
Application Number:
20140112084
A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.
Remapping Memory Cells Based on Future Endurance Measurements
Granted: April 24, 2014
Application Number:
20140115296
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory…
INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO CHANGE A CLOCK SIGNAL FREQUENCY WHILE A DATA SIGNAL IS VALID
Granted: April 24, 2014
Application Number:
20140112089
Methods and apparatuses for communicating information are described. In some embodiments, a first integrated circuit (IC) provides a clock signal and a data signal to a second IC, wherein the data bits of the data signal are timed according to the clock signal, and wherein the frequency of the clock signal is capable of being changed even when the data signal is valid.
MEMORY SYSTEM FOR ERROR DETECTION AND CORRECTION COVERAGE
Granted: April 17, 2014
Application Number:
20140108889
A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the…
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
Granted: April 17, 2014
Application Number:
20140104935
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die…
DATA BUFFER WITH A STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE
Granted: April 10, 2014
Application Number:
20140101382
A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.
Memory Controller That Enforces Strobe-To-Strobe Timing Offset
Granted: April 10, 2014
Application Number:
20140098622
A memory controller outputs a clock signal to first and second DRAMs disposed on a memory module, the clock signal requiring respective first and second time intervals to propagate to the first and second DRAMs. The memory controller outputs a write command to be sampled by the first and second DRAMs at times indicated by the first clock signal and outputs, in association with the write command, first and second write data to the first and second DRAMs, respectively. The memory…
ARTICLE OF MANUFACTURE WITH MICRO-FEATURES OF DIFFERING SURFACE ROUGHNESS
Granted: April 10, 2014
Application Number:
20140098566
An article of manufacture includes first and second micro-features of well-defined shape. In some embodiments, the article of manufacture is a light guide or redirecting film and the second micro-features are micro-optical elements configured to disrupt a specular optical path that includes the second micro-optical element. In other embodiments, the article of manufacture is a patterning tool for use in making an optical substrate. Embodiments of the optical substrate are formed by…
LED FLASHLIGHT
Granted: April 3, 2014
Application Number:
20140092590
A flashlight includes first and second solid-state light sources, a collimating optical element, and a light guide. Light output by the first light source interacts with the collimating optical element to output a light from the flashlight along an optical axis of the collimating optical element. The light guide includes an outer major surface, a first end, a second end, a longitudinal axis extending between the first end and the second end, and a light input edge at the first end. Light…
LED LAMP AND LED LIGHTING ASSEMBLY
Granted: April 3, 2014
Application Number:
20140092580
An LED lamp or LED lighting assembly includes a light guide having opposed major surfaces configured to propagate light by total internal reflection and a light input edge extending between the major surfaces. A light source is adjacent to the light input edge and is configured to edge light the light guide. In some embodiments, the light source is moveable relative to the light input edge, and the spectrum of the light output from the light guide may be adjusted by movement of the light…
COMMUNICATION VIA A MEMORY INTERFACE
Granted: March 20, 2014
Application Number:
20140082234
A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to…
INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY
Granted: March 13, 2014
Application Number:
20140070854
Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first…
RECONFIGURABLE OPTICAL DEVICE USING A TOTAL INTERNAL REFLECTION (TIR) OPTICAL SWITCH
Granted: March 13, 2014
Application Number:
20140071329
An optical device having a total internal reflection (TIR) switch is able to switch to form two different optical imaging paths. Each optical imaging path has different optical characteristics that causes a detector to capture different imagery depending upon which optical imaging path is used. The TIR switch is switchable between a TIR state and a transmission state to control which optical imaging path is used by the device for imaging.
