Serial link receiver with improved bandwidth and accurate eye monitor
Granted: November 23, 2021
Patent Number:
11184198
A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction…
Burst-tolerant decision feedback equalization
Granted: November 23, 2021
Patent Number:
11184197
A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between…
High-resolution digitally controlled delay line
Granted: November 23, 2021
Patent Number:
11183995
In a delay control circuit having a plurality of series-coupled delay stages, an input signal is routed through one of the series-coupled delay stages via a first delay element if a first delay control value is in a first state, the first delay element imposing a first signal propagation delay according to a first bias signal. If the delay control value is in a second state, the input signal is routed through the one of the series-coupled delay stages via a second delay element instead…
Using a stuttered clock signal to reduce self-induced voltage noise
Granted: November 23, 2021
Patent Number:
11181941
The disclosed embodiments relate to a technique that uses a modified timing signal to reduce self-induced voltage noise in a synchronous system. During a transient period associated with a deterministic event in the synchronous system, the technique uses a modified timing signal generated based on a normal timing signal as a timing signal for the synchronous system. Outside of the transient period, the technique uses the normal timing as the timing signal for the synchronous system. In…
Wear leveling in a memory system
Granted: November 16, 2021
Patent Number:
11176037
Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.
Stacked semiconductor device
Granted: November 9, 2021
Patent Number:
11170842
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on…
High-speed signaling systems with adaptable pre-emphasis and equalization
Granted: November 2, 2021
Patent Number:
11165613
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without…
Variable width memory module supporting enhanced error detection and correction
Granted: November 2, 2021
Patent Number:
11164622
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
Secure logic locking and configuration with camouflaged programmable micro netlists
Granted: November 2, 2021
Patent Number:
11163930
The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.
Methods and circuits for adaptive equalization
Granted: October 19, 2021
Patent Number:
11153133
An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.
Memory error detection
Granted: October 19, 2021
Patent Number:
11150982
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a…
Low power cryogenic switch
Granted: October 12, 2021
Patent Number:
11146269
An signal switching integrated-circuit die includes an array of switch cells, control signal contacts, data input contacts and data output contacts. Switch control signals are received from an external control-signal source via respective control signal contacts, inbound data signals are received from one or more external data-signal sources via respective data input contacts and outbound data signals are conveyed to one or more external data-signal destinations via respective data…
Transmit driver architecture
Granted: October 5, 2021
Patent Number:
11139842
A method and related apparatus for outputting an analog signal are disclosed. A plurality of transmit levels corresponding to respective predetermined equalization levels is provided. A stream of digital signals carrying data is provided. A transmit level from among the plurality of transmit levels based on the digital signals carrying data is selected. The selected transmit level is received, the selected transmit level is converted to an analog signal of the selected transmit level,…
Transmitter/receiver with small-swing level-shifted output
Granted: September 28, 2021
Patent Number:
11133843
An integrated-circuit output driver generates, in response to an input signal constrained to a first voltage range, a control signal at one of two voltage levels according to a data bit conveyed in the input signal, the two voltages levels defining upper and lower levels of a second voltage range substantially larger than the first voltage range. The output driver generates an output-drive signal constrained to a third voltage range according to the one of the two voltage levels of the…
Receiver training of reference voltage and equalizer coefficients
Granted: September 28, 2021
Patent Number:
11133081
In a receiver having at least a first equalizer and a sampler, a calibration module jointly calibrates a reference voltage and one or more equalizer coefficients. For each of a set of test reference voltages, an equalizer coefficient for the first equalizer may be learned that maximizes a right eye boundary of an eye diagram of a sampler input signal to a sampler of the receiver following the equalization stage. Then, from the possible pairs of reference voltages and corresponding…
High level instructions with lower-level assembly code style primitives within a memory appliance for accessing memory
Granted: September 28, 2021
Patent Number:
11132328
A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to said memory unit controller. The memory related command is translated by the processor into a plurality of commands that are formatted to perform prescribed data manipulation operations on…
Low latency memory access
Granted: September 28, 2021
Patent Number:
11132307
A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can…
Signal receiver with skew-tolerant strobe gating
Granted: September 21, 2021
Patent Number:
11127444
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe…
Image sensor having sub-diffraction-limit pixels
Granted: September 21, 2021
Patent Number:
11128831
An imaging system has an imager comprising a plurality of jots. A readout circuit is in electrical communication with the imager. The readout circuit can be configured to facilitate the formation of an image by defining neighborhoods of the jots, wherein a local density of exposed jots within a neighborhood is used to generate a digital value for a pixel of the image.
Communication channel calibration using feedback
Granted: September 21, 2021
Patent Number:
11128388
A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component…
