Signal receiver with skew-tolerant strobe gating
Granted: September 21, 2021
Patent Number:
11127444
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe…
System and method for memory access in server communications
Granted: September 14, 2021
Patent Number:
11121904
Embodiments of the present invention are directed to memories used in server applications. More specifically, embodiments of the present invention provide a server system has a memory management module that is connected to a processor, a memory module, and a network interface. The memory management module is configured to allocate a first channel to access the memory module for local memory accesses by the processor and communicate first data blocks between the memory module and the…
Direct sequence detection and equalization
Granted: September 14, 2021
Patent Number:
11121894
Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence…
Equalizing transmitter and method of operation
Granted: September 14, 2021
Patent Number:
11121893
A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel.
Methods and circuits for asymmetric distribution of channel equalization between devices
Granted: September 7, 2021
Patent Number:
11115247
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the…
Signaling system with adaptive timing calibration
Granted: September 7, 2021
Patent Number:
11115179
A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the…
Memory system with multiple open rows per bank
Granted: September 7, 2021
Patent Number:
11114150
A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the…
Memory mirroring
Granted: August 31, 2021
Patent Number:
11106542
Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses…
Memory subsystem for a cryogenic digital system
Granted: August 31, 2021
Patent Number:
11109512
The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.
Communication channel calibration for drift conditions
Granted: August 31, 2021
Patent Number:
11108510
A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received…
Synchronous wired-OR ACK status for memory with variable write latency
Granted: August 24, 2021
Patent Number:
11101393
A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the…
Memory controller with clock-to-strobe skew compensation
Granted: August 24, 2021
Patent Number:
11100976
An integrated circuit device outputs a sequence of differently delayed calibration data timing signals to a DRAM component via a data-signal timing line as part of a timing calibration operation and then stores a delay value, based on at least one of the calibration data timing signals, that compensates for a difference in signal propagation times over the data-signal timing line and a command/address-signal timing line. After the timing calibration operation, the integrated circuit…
Phase modulated data link for low-swing wireline applications
Granted: August 10, 2021
Patent Number:
11088880
A communication system comprises a transmitter and a receiver that communicate differential phase modulated data over a wireline channel pair. The transmitter encodes data symbols by generating first and second data signals with differentially phase shifted signal transitions with respect to one another. The receiver receives the first data signal and the second data signal and samples the first data signal based on a signal transition timing of the second data signal to generate a first…
Structure for delivering power
Granted: August 3, 2021
Patent Number:
11083077
A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated…
Adaptive equalization using correlation of data patterns with errors
Granted: August 3, 2021
Patent Number:
11082268
An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data…
Hybrid memory module
Granted: August 3, 2021
Patent Number:
11080185
A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.
Error coalescing
Granted: August 3, 2021
Patent Number:
11080137
A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic…
Configurable, power supply voltage referenced single-ended signaling with ESD protection
Granted: July 27, 2021
Patent Number:
11075671
A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.
Memory system using asymmetric source-synchronous clocking
Granted: July 20, 2021
Patent Number:
11068017
The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as…
Memory module with emulated memory device population
Granted: July 20, 2021
Patent Number:
11068161
In a memory module having a plurality of discrete memory die packages, an N-bit data interface and a command/address buffer, a memory access command and chip-select input signals are received within the command/address buffer. In response to the chip-select input signals, the command/address buffer outputs chip-select output signals greater in quantity than the chip-select input signals to exclusively enable one of a plurality of groups of the discrete memory die packages to respond to…
