Verify before program resume for memory devices
Granted: July 20, 2021
Patent Number:
11068388
A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively…
Dual-domain combinational logic circuitry
Granted: July 20, 2021
Patent Number:
11068237
A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit…
Memory module with emulated memory device population
Granted: July 20, 2021
Patent Number:
11068161
In a memory module having a plurality of discrete memory die packages, an N-bit data interface and a command/address buffer, a memory access command and chip-select input signals are received within the command/address buffer. In response to the chip-select input signals, the command/address buffer outputs chip-select output signals greater in quantity than the chip-select input signals to exclusively enable one of a plurality of groups of the discrete memory die packages to respond to…
Memory system using asymmetric source-synchronous clocking
Granted: July 20, 2021
Patent Number:
11068017
The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as…
Fault tolerant memory systems and components with interconnected and redundant data interfaces
Granted: July 13, 2021
Patent Number:
11061773
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around…
Receiver with clock recovery circuit and adaptive sample and equalizer timing
Granted: July 13, 2021
Patent Number:
11063791
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the…
Phase control block for managing multiple clock domains in systems with frequency offsets
Granted: July 13, 2021
Patent Number:
11063741
A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect…
Strobe acquisition and tracking
Granted: July 13, 2021
Patent Number:
11062748
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in…
System and method for providing a configurable timing control for a memory system
Granted: July 13, 2021
Patent Number:
11062743
A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output…
System and method for implementing a multi-threaded device driver in a computer system
Granted: July 13, 2021
Patent Number:
11061841
A method of implementing a multi-threaded device driver for a computer system is disclosed. A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted…
Transmitter with self-triggered transition equalizer
Granted: July 6, 2021
Patent Number:
11057247
A transmitting device includes an output node, at least one driver circuit and transition equalization circuitry. The driver circuit drives an output data signal including a data transition onto the output node. The output of the transition equalization circuitry is coupled to the output node. The transition equalization circuitry begins to drive the output node at the data transition and ends driving of the output node a pre-determined delay after beginning to drive the output node. The…
Network interface with timestamping and data protection
Granted: June 29, 2021
Patent Number:
11050500
In a general aspect, a network transmission interface can include, within an egress data path, a physical coding sublayer (PCS) operating in a constant bitrate domain for transmitting data frames on a network link; a timestamp unit configured to insert timestamps in payloads of the frames; a transmission media access control (MAC) unit located at a boundary between the constant bitrate domain and a variable bitrate domain, configured to receive the frames at a variable bitrate,…
Memory component with command-triggered data clock distribution
Granted: June 29, 2021
Patent Number:
11049546
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
Memory module and system supporting parallel and serial access modes
Granted: June 29, 2021
Patent Number:
11049532
A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency,…
Distributed procedure execution and file systems on a memory interface
Granted: June 29, 2021
Patent Number:
11048410
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be…
Memory module with programmable command buffer
Granted: June 22, 2021
Patent Number:
11042492
A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the…
Countermeasures against an attack by analysis of electrical consumption for a cryptographic device
Granted: June 22, 2021
Patent Number:
11044073
In a general aspect, a countermeasure method implemented in a microcircuit can include selecting, at each cycle of a clock signal, a supply mode of a component internal to the microcircuit, the supply mode can be selected from among a first supply mode in which the component is fully supplied by a first supply circuit connected to a supply input of the microcircuit, and at least one second supply mode in which the component is at least partially supplied by a second supply circuit…
Memory system topologies including a memory die stack
Granted: June 22, 2021
Patent Number:
11043258
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address…
High-throughput low-latency hybrid memory module
Granted: June 15, 2021
Patent Number:
11036398
Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during…
Systems and methods for improving resolution in lensless imaging
Granted: June 15, 2021
Patent Number:
11035989
An imaging system includes a phase grating overlying a two-dimensional array of pixels, which may be thermally sensitive pixels for use in infrared imaging. The phase grating comprises a two-dimensional array of identical subgratings that define a system of Cartesian coordinates. The subgrating and pixel arrays are sized and oriented such that the pixels are evenly distributed with respect to the row and column intersections of the subgratings. The location of each pixel thus maps to a…
