Load reduced memory module
Granted: January 14, 2025
Patent Number:
12200860
The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset…
Low power edge and data sampling
Granted: January 14, 2025
Patent Number:
12200096
An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.
Memory controllers, systems, and methods supporting multiple request modes
Granted: January 14, 2025
Patent Number:
12198780
A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The…
Memory system with threaded transaction support
Granted: January 14, 2025
Patent Number:
12197731
Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling…
Deferred fractional memory row activation
Granted: January 7, 2025
Patent Number:
12190990
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
DRAM retention test method for dynamic error correction
Granted: January 7, 2025
Patent Number:
12190974
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
Buffer IC with asymmetric memory module interfaces
Granted: January 7, 2025
Patent Number:
12189548
An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket.
Command-differentiated storage of internally and externally sourced data
Granted: January 7, 2025
Patent Number:
12189523
A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.
Page table manager
Granted: December 24, 2024
Patent Number:
12174749
The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page…
Stacked DRAM device and method of manufacture
Granted: December 17, 2024
Patent Number:
12170126
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory…
Methods and circuits for slew-rate calibration
Granted: December 10, 2024
Patent Number:
12166485
Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.
Memory-integrated neural network
Granted: December 10, 2024
Patent Number:
12165047
An integrated-circuit neural network includes chain of multiply-accumulate units co-located with a high-bandwidth storage array. Each multiply accumulate includes a digital input port, analog input port and multiply-adder circuitry. The digital input port receives a matrix of digital-weight values from the storage array and the analog input port receives a counterpart matrix of analog input signals, each analog input signal exhibiting a respective electronic current representative of…
Quad-data-rate (QDR) host interface in a memory system
Granted: December 10, 2024
Patent Number:
12164808
Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes…
Off-module data buffer
Granted: December 10, 2024
Patent Number:
12164447
In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces…
Clock buffer
Granted: November 26, 2024
Patent Number:
12155391
A phase-locked loop or delay locked loop provides a coarse alignment between an input clock and an output clock. A latch receiver circuit provides an indicator of a delay error between the input clock and the output clock. The delay error is used by a control circuit or state machine to adjust a fine delay that affects the output clock signal timing relative to the input clock signal. The fine delay is adjusted to minimize the timing difference between the output clock signal and the…
Power management integrated circuit device having multiple initialization/power up modes
Granted: November 19, 2024
Patent Number:
12147285
Disclosed are techniques for a power management integrated circuit (PMIC) to support a power-up sequence from a powered-down state to a powered-up state when both a main supply voltage and a backup supply voltage are present or when only the backup supply voltage is present. The PMIC may monitor the two supply voltages to identify the supply voltages that are present. The PMIC may be configured with a power-up initialization mode of operation through an EFUSE/MTP register, including a…
High capacity memory system using standard controller component
Granted: November 19, 2024
Patent Number:
12148462
The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.
Deterministic operation of storage class memory
Granted: November 19, 2024
Patent Number:
12147362
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value…
Heterogenous-latency memory optimization
Granted: November 19, 2024
Patent Number:
12147351
Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are…
Managing memory maintenance operations in a memory system having backing storage media
Granted: November 19, 2024
Patent Number:
12147345
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease…
