Signal receiver with skew-tolerant strobe gating
Granted: August 13, 2024
Patent Number:
12062413
A first-in-first-out (FIFO) storage structure within an integrated-circuit component is loaded with qualification values corresponding to respective pairs of edges expected within a timing strobe signal transmitted to the integrated-circuit component. The qualification values are sequentially output from the FIFO storage structure during respective cycles of the timing strobe signal and a gate signal is either asserted or deasserted during the respective cycles of the timing strobe…
Memory controller systems with nonvolatile memory for storing operating parameters
Granted: July 30, 2024
Patent Number:
12050787
The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory.…
Energy-efficient error-correction-detection storage
Granted: July 30, 2024
Patent Number:
12050513
A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without…
Buffer circuit with adaptive repair capability
Granted: July 16, 2024
Patent Number:
12040035
A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second…
Methods and circuits for power management of a memory module
Granted: July 9, 2024
Patent Number:
12033683
A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of…
Memory controller partitioning for hybrid memory system
Granted: July 9, 2024
Patent Number:
12032845
A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict…
Interface clock management
Granted: July 9, 2024
Patent Number:
12032508
The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller…
Memory controller with error detection and retry modes of operation
Granted: July 2, 2024
Patent Number:
12026038
A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data…
Signal skew in source-synchronous system
Granted: July 2, 2024
Patent Number:
12027197
A memory controller integrated circuit includes a clock signal generator circuit configured to generate a plurality of strobe signals. The memory controller integrated circuit further includes a memory interface circuit coupled to the clock signal generator circuit, the memory interface circuit configured to transmit the plurality of strobe signals to a memory module, wherein each of the plurality of strobe signals is offset with respect to an adjacent strobe signal, and transmit a…
Multiple precision memory system
Granted: July 2, 2024
Patent Number:
12026104
Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays.…
Memory device having non-uniform refresh
Granted: June 25, 2024
Patent Number:
12020740
An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.
High capacity, high performance memory system
Granted: June 18, 2024
Patent Number:
12014089
Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that…
Local internal discovery and configuration of individually selected and jointly selected devices
Granted: June 11, 2024
Patent Number:
12007916
A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the…
On-die termination of address and command signals
Granted: June 4, 2024
Patent Number:
12002540
A memory device includes a set of inputs, and a first register that includes a first register field to store a value for enabling application of one of a plurality of command/address (CA) on-die termination (ODT) impedance values to first inputs that receive the CA signals; and a second register field to store a value for enabling application of one of a plurality of chip select (CS) ODT impedance values to a second input that receives the CS signal. A third register field may store a…
Command/address channel error detection
Granted: June 4, 2024
Patent Number:
12002532
A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed,…
Self-annealing data storage system
Granted: June 4, 2024
Patent Number:
12002513
Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second…
Buffered dynamic random access memory device
Granted: June 4, 2024
Patent Number:
12002506
A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired…
Multi-modal refresh of dynamic, random-access memory
Granted: June 4, 2024
Patent Number:
12001697
A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized…
Energy efficient storage of error-correction-detection information
Granted: June 4, 2024
Patent Number:
12001283
Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row.…
Optimizing power in a memory device
Granted: May 28, 2024
Patent Number:
11994930
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at…
