Low power memory control with on-demand bandwidth boost
Granted: May 28, 2024
Patent Number:
11996164
Within a memory control component, command/address circuitry transmits a first command/address value to a memory component during a first interval and a second command/address value to the memory component during a second interval, and timing circuitry transmits a data strobe to the memory component during the first interval and a data clock to the memory component during the second interval. The timing circuitry transitions the data strobe from a parked state to a toggling state during…
Low power signaling interface
Granted: May 28, 2024
Patent Number:
11996160
In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface…
Optimizing power in a memory device
Granted: May 28, 2024
Patent Number:
11994930
Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at…
Data transmission using delayed timing signals
Granted: May 21, 2024
Patent Number:
11990912
An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external…
Multi-die memory device
Granted: May 21, 2024
Patent Number:
11990177
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array…
Method of securing a comparison of data during the execution of a program
Granted: May 21, 2024
Patent Number:
11989609
This disclosure relates to a method for securing the execution of a program by a processor, including a comparison instruction for comparing two data items, followed by a program operation which is selected as a function of a comparison result provided by the comparison instruction. The method may include, before the execution of the comparison instruction, calculating in various ways comparison data representative of the equality of the data to be compared, after the execution of the…
Memory module with persistent calibration
Granted: May 21, 2024
Patent Number:
11989430
A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and…
Memory system with independently adjustable core and interface data rates
Granted: May 14, 2024
Patent Number:
11983137
An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.
Drift detection in timing signal forwarded from memory controller to memory device
Granted: May 14, 2024
Patent Number:
11983031
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device…
Serial presence detect reliability
Granted: May 7, 2024
Patent Number:
11977442
A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C…
Synchronous wired-or ACK status for memory with variable write latency
Granted: April 30, 2024
Patent Number:
11973153
A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the…
Load-reduced DRAM stack
Granted: April 30, 2024
Patent Number:
11972121
Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.
Variable width memory module supporting enhanced error detection and correction
Granted: April 23, 2024
Patent Number:
11967364
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
Load reduced memory module
Granted: April 16, 2024
Patent Number:
11963299
The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset…
Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture
Granted: April 16, 2024
Patent Number:
11960438
A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding…
Semiconductor memory systems with on-die data buffering
Granted: April 16, 2024
Patent Number:
11960418
A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die…
Memory controller with looped-back calibration data receiver
Granted: April 16, 2024
Patent Number:
11960344
A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more…
Memory module register access
Granted: April 9, 2024
Patent Number:
11953981
During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not…
Memories and memory components with interconnected and redundant data interfaces
Granted: April 9, 2024
Patent Number:
11955165
A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of…
Command-triggered data clock distribution mode
Granted: April 9, 2024
Patent Number:
11955161
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
