NUCLEIC ACID SEQUENCING BY SYNTHESIS USING MAGNETIC SENSOR ARRAYS
Granted: January 9, 2025
Application Number:
20250010293
Methods of detecting molecules using an apparatus comprising a plurality of magnetic sensors are disclosed. A method may include binding a first molecule to a proximal wall of a fluid chamber of the apparatus, and adding, to the fluid chamber, a magnetically-labeled molecule comprising a cleavable magnetic label, wherein the magnetically-labeled molecule is configured to bind to or be incorporated by the first molecule. The method may use at least one address line and at least one…
SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLING
Granted: January 2, 2025
Application Number:
20250004660
A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also,…
Configurable Arithmetic HW Accelerator
Granted: December 26, 2024
Application Number:
20240427521
A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a…
Data Storage With Real Time Dynamic Clock Frequency Control
Granted: December 26, 2024
Application Number:
20240427407
The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage…
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
Granted: November 28, 2024
Application Number:
20240395328
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
MODELLING AND PREDICTION OF VIRTUAL QUALITY CONTROL DATA INCORPORATING AREA LOCATION IN THE PRODUCTION OF MEMORY DEVICES
Granted: November 21, 2024
Application Number:
20240387295
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests.
Data Integrity Protection Of SSDs Utilizing Streams
Granted: November 7, 2024
Application Number:
20240370195
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of streams. When a write command is received to write data to a stream, change log data is generated and stored in the RAM1, the previous delta data for the stream is copied from the RAM2 to the RAM1 to be updated with the change log data,…
Zoned Namespaces in Solid-Stage Drives
Granted: November 7, 2024
Application Number:
20240370178
The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller and a media unit. The capacity of the media unit is divided into a plurality of zones. The controller is configured to make informed use of errors by update zone metadata to indicate one or more first logical block addresses were skipped and to indicate the next valid logical block address is available to store data. The controller is further configured to update…
Embedded PHY (EPHY) IP Core for FPGA
Granted: November 7, 2024
Application Number:
20240369628
The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYS (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC)…
MINI-PUMP LEVEL SHIFTER FOR ROBUST SWITCHING OPERATION UNDER LOW VDD ENVIRONMENT
Granted: October 31, 2024
Application Number:
20240364338
On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter…
NEGATIVE WORD LINE ENABLED PRE-BOOSTING STRATEGY TO IMPROVE NAND PROGRAM PERFORMANCE
Granted: October 24, 2024
Application Number:
20240355401
To improve programming performance in NAND memory, while maintaining programming accuracy and reducing program disturb, the channel pre-charge phase before a programming pulse can be eliminated. Instead, a read recovery phase after the program verify directly discharges a selected word line from the verify voltage to a negative word line voltage, with non-selected word lines being directly discharged from the read bypass voltage to the negative word line voltage. From the negative word…
SEPARATE PEAK CURRENT CHECKPOINTS FOR CLOSED AND OPEN BLOCK READ ICC COUNTERMEASURES IN NAND MEMORY
Granted: October 24, 2024
Application Number:
20240355400
To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the…
Data Storage Device and Method for Device-Initiated Hibernation
Granted: October 24, 2024
Application Number:
20240354033
A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase…
NOISE REDUCTION IN SENSE AMPLIFIERS FOR NON-VOLATILE MEMORY
Granted: October 3, 2024
Application Number:
20240331741
Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the…
NON-VOLATILE MEMORY WITH SLOW VOLTAGE RAMP COMPENSATION
Granted: September 26, 2024
Application Number:
20240321379
Non-volatile memory cells are programmed by raising a voltage applied to a selected word line to a program voltage during a first time period of a programming process for selected non-volatile memory cells connected to the selected word line; programming the selected non-volatile memory cells using the program voltage during a second time period after the first time period; testing, during the first time period, whether the voltage applied to the selected word line is greater than one or…
ONE-TIME PROGRAMMABLE MEMORY DEVICES AND METHODS
Granted: September 26, 2024
Application Number:
20240321371
An apparatus is provided that includes a memory cell having a reversible resistance-switching memory element coupled in series with a selector element. The selector element has a first resistance. The resistance-switching memory element is configured to reversibly switch between a second resistance and a third resistance. The memory cell may be selectively configured as either a re-writeable memory cell or a one-time programmable memory cell. The memory cell functions as a one-time…
NON-VOLATILE MEMORY WITH ADAPTING ERASE PROCESS
Granted: September 26, 2024
Application Number:
20240319905
A memory system performs an erase process for the non-volatile memory cells including performing erase verify for the non-volatile memory cells. The erase verify comprises comparing threshold voltages of the non-volatile memory cells to an erase verify reference voltage and determining whether an amount of the non-volatile memory cells having a threshold voltage greater than the erase verify reference voltage is less than an allowed bit count. During the erase process, the system…
HOLE CHANNEL PRE-CHARGE TO ENABLE LARGE-VOLUME IN-PLACE DATA SANITIZATION OF NON-VOLATILE MEMORY
Granted: September 26, 2024
Application Number:
20240319888
In NAND memory, data sanitization allows a relatively small unit of data (e.g., less than a block) to be effectively destroyed by increasing threshold voltages of memory cells from their programmed threshold voltage to the highest threshold state. To reduce the amount of disturb on memory cells not selected for data sanitization, prior to applying a program voltage to a target word line, a hole based pre-charge operation is performed. More specifically, for NAND strings having a memory…
OPEN BLOCK READ ICC REDUCTION
Granted: August 29, 2024
Application Number:
20240290395
Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude…
NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING
Granted: August 29, 2024
Application Number:
20240290412
As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the…
