Sandisk Patent Applications

Storage System and Method for Recovering Data Corrupted in a Host Memory Buffer

Granted: October 19, 2017
Application Number: 20170300246
A storage system and method for recovering data corrupted in a host memory buffer are provided. In one embodiment, a storage system is provided comprising a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to receive a logical-to-physical map from a volatile memory of a host for storage in the storage system's non-volatile memory; determine if there is an error in an entry in the logical-to-physical map; in response to…

MEMORY INTERFACE COMMAND QUEUE THROTTLING

Granted: October 19, 2017
Application Number: 20170300263
A storage device with a memory may implement command throttling in order to control power usage. The throttling may be based on modifications of certain memory parameters, such as a reduction in clock rate, bus speed, operating voltage, or command type changes. The throttling may be performed at a back end or memory interface of the storage device such that the memory interface receives un-throttled commands and can optimally throttle all of the commands from the front end.

Dummy Voltage To Reduce First Read Effect In Memory

Granted: October 19, 2017
Application Number: 20170301403
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read…

FILAMENT CONFINEMENT IN REVERSIBLE RESISTANCE-SWITCHING MEMORY ELEMENTS

Granted: October 5, 2017
Application Number: 20170287557
A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a…

NAND STRUCTURE WITH TIER SELECT GATE TRANSISTORS

Granted: October 5, 2017
Application Number: 20170287566
Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a…

System and Method for Erase Detection before Programming of a Storage Device

Granted: October 5, 2017
Application Number: 20170287568
Systems and methods for detecting program disturb and for programming/reading based on the detected program disturb are disclosed. Program disturb comprises unintentionally programming an unselected section of memory during the program operation of the selected section of memory. To reduce the effect of program disturb, the section of memory is analyzed in a predetermined state (such as the erase state) for program disturb. In response to identifying signs of program disturb, the…

OUT OF ORDER READ TRANSFER WITH HOST MEMORY BUFFER

Granted: October 5, 2017
Application Number: 20170285940
A storage device may utilize a host memory buffer for re-ordering commands in a submission queue. Out of order commands in a submission queue that uses host virtual buffers that are not the same size may be difficult to search. Accordingly, commands in a submission queue may be correctly ordered in a host memory buffer before being put into the host virtual buffers. When the commands are in order, the search operation for specific data is improved.

METHOD AND SYSTEM FOR MANAGING DATA IN NON-VOLATILE MEMORY

Granted: October 5, 2017
Application Number: 20170285948
Methods and systems for managing data storage in a non-volatile memory system are disclosed. The method may include receiving data, determining a data classification for the received data from a predetermined plurality of data classifications, writing the received data to an open block having only data of a same data classification as the determined data classification and, upon completely programming the open block, associating an epoch indicator where the epoch indicator defines a time…

METHOD AND SYSTEM FOR COMPACTING DATA IN NON-VOLATILE MEMORY

Granted: October 5, 2017
Application Number: 20170286291
A system and method for compacting data in a non-volatile memory system that may reduce the need for control data updates is described. The method may include copying valid data from a source block to a destination block, and also writing new host data to the destination block, such that the offset position in the destination block of the copied data is the same as in the source block and fewer mapping table updates are needed for the copied data. The system may include a non-volatile…

SHALLOW TRENCH ISOLATION TRENCHES AND METHODS FOR NAND MEMORY

Granted: September 28, 2017
Application Number: 20170278926
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench has a first tab extension and a second tab extension. The first tab extension is disposed at a top portion of the shallow trench isolation trench, and extends in a first direction from the shallow trench isolation trench. The second tab extension is disposed at a top portion of…

DATA REGISTER COPYING FOR NON-VOLATILE STORAGE ARRAY OPERATIONS

Granted: September 21, 2017
Application Number: 20170269856
Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from…

Hybrid Checkpointed Memory

Granted: September 21, 2017
Application Number: 20170270041
Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. An extended memory module uses volatile memory of a host and a non-volatile memory medium as virtual memory for the host. A clone module clones data of a range of virtual memory in response to a checkpoint event for the range of virtual memory. A range of virtual memory may include data stored in a volatile memory and data stored in a non-volatile memory medium. A checkpoint module…

Vertical Resistor In 3D Memory Device With Two-Tier Stack

Granted: September 14, 2017
Application Number: 20170263642
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends…

Voltage Regulator With Fast Overshoot Settling Response

Granted: September 7, 2017
Application Number: 20170255215
A voltage regulator circuit is provided in which voltage overshoots are quickly dissipated using a discharge path which is connected to an output of the voltage regulator. Circuitry for controlling the discharge path is provided using internal currents of an error amplifier to provide a space-efficient and power-efficient design with a fast response. Moreover, hysteresis can be provided to avoid toggling between discharge and no discharge, and to avoid undershoot when discharging the…

MULTI-TYPE PARITY BIT GENERATION FOR ENCODING AND DECODING

Granted: September 7, 2017
Application Number: 20170255512
A non-volatile memory system may be configured to generate a codeword with first-type parity bits and one or more second-type parity bits. If a storage location in which the codeword is to be stored includes one or more bad memory cells, the bit sequence of the codeword may be arranged so that at least some of the second-type parity bits are stored in the bad memory cells. During decoding, a first set of syndrome values may be determined for a first set of check nodes and a second set of…

SKELETON I/O GENERATION FOR EARLY ESD ANALYSIS

Granted: September 7, 2017
Application Number: 20170255741
A design flow of an integrated circuit may include a skeleton input/output (I/O) generation stage during which information about ESD protection circuitry and rails but not functional circuitry of the I/O cells of the integrated circuit is generated. The information may be used in an ESD analysis stage to generate performance characteristics of the ESD protection circuitry. Results of the ESD analysis may then be used to design optimized ESD protection circuitry along with the rest of the…

Techniques For Programming Of Select Gates In NAND Memory

Granted: September 7, 2017
Application Number: 20170256317
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set…

Adaptive Determination Of Program Parameter Using Program Of Erase Rate

Granted: September 7, 2017
Application Number: 20170256320
Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In one approach, a count of pulses used to program the cells to different verify levels of respective data states is stored. A slope of a straight line fit of data points is then obtained. Each data point can include one of the verify levels and a corresponding one of the counts. An optimal step size is determined based on the slope.…

DYNAMIC-SHIFTING REDUNDANCY MAPPING FOR NON-VOLATILE DATA STORAGE

Granted: September 7, 2017
Application Number: 20170256328
Apparatuses, systems, methods, and computer program products are disclosed for redundancy mapping. A controller is configured to determine that one or more defects affect a subset of a first group of cells and a subset of a second group of cells of a non-volatile memory medium. A non-volatile memory medium may include a plurality of groups of cells, and redundant groups of cells may be available for replacing defective groups of cells. A controller is configured to store a mapping…

Efficient Peak Current Management In A Multi-Die Stack

Granted: September 7, 2017
Application Number: 20170256955
Techniques for managing the distribution of power among competing electronic devices such as semiconductor die are presented. Each device may be connected to a common power supply and sources a current on a load bus based on an estimated current consumption of a next desired state. However, before doing this, the device performs an internal check to determine whether there is a sufficient available current. The device decreases a logical value of the system current specification by the…