STAGE BASED FREQUENCY OPTIMIZATION FOR AREA REDUCTION OF CHARGE PUMPS
Granted: August 22, 2024
Application Number:
20240283359
A stage-based frequency optimization for a charge pump achieves a higher area efficiency by operating different stages of the charge pump at their optimized frequency simultaneously, instead of single common frequency, to obtain greater output strength. A first set of stages uses triple well devices as transfer switches and operates at a first, higher frequency. The first stages supply a second set of stages using high voltage devices as transfer switches and operates at a second, lower…
ENHANCED OPERATIONS OF NON-VOLATILE MEMORY WITH SHARED DATA TRANSFER LATCHES
Granted: August 22, 2024
Application Number:
20240282392
An apparatus includes a control circuit that is configured to connect to an array of non-volatile memory cells. The control circuit includes a first plurality of data latches configured to connect to non-volatile memory cells of a first plane and a second plurality of data latches configured to connect to non-volatile memory cells of a second plane. The control circuit also includes a shared data transfer data latch configured for transfer of data with the first plurality of data latches…
INTEGRATED MEMORY AND CONTROL DIES
Granted: August 15, 2024
Application Number:
20240276740
A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise…
SINGLE-LEVEL CELL PUMP SKIP PROGRAM OPERATION PRELIMINARY PERIOD TIMING OPTIMIZATION FOR NON-VOLATILE MEMORY
Granted: August 15, 2024
Application Number:
20240274200
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the word lines and the strings and is configured to successively apply one of a series of pulses of a program voltage to each selected one of the word lines to program the memory cells connected thereto during a program…
STACKED COLUMN FLOORPLAN FOR NAND
Granted: August 15, 2024
Application Number:
20240274192
Technology is disclosed herein for memory device with control circuitry having an efficient floorplan. Control circuitry resides in a control semiconductor die that is bonded to a memory die NAND strings extending in a z-direction. The memory die has bit lines extending across the NAND strings in an x-direction. First column control circuitry is connected to and configured to control a first set of bit lines. Second column control circuitry is connected to and configured to control a…
CROSS-POINT ARRAY REFRESH SCHEME
Granted: August 8, 2024
Application Number:
20240265958
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However,…
APPARATUS AND METHOD FOR SELECTIVELY REDUCING CHARGE PUMP SPEED DURING ERASE OPERATIONS
Granted: August 1, 2024
Application Number:
20240257878
An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on…
MULTI-WAFER BONDING FOR NAND SCALING
Granted: July 25, 2024
Application Number:
20240250007
Technology is disclosed herein for a memory device with multiple dies bonded together. The memory device may be referred to herein as an integrated memory assembly. The integrated memory assembly has a control semiconductor die and two or more memory semiconductor dies. In one embodiment, each memory semiconductor die has a memory structure having blocks of memory cells. Bit lines extend over the respective memory structure. In one embodiment the integrated memory assembly has what is…
PROGRAMMING TECHNIQUES IN A MEMORY DEVICE TO REDUCE A HYBRID SLC RATIO
Granted: July 18, 2024
Application Number:
20240242764
The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is…
NON-VOLATILE MEMORY WITH SMART CONTROL OF OVERDRIVE VOLTAGE
Granted: July 11, 2024
Application Number:
20240233847
A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.
NON-VOLATILE MEMORY WITH LOWER CURRENT PROGRAM-VERIFY
Granted: July 11, 2024
Application Number:
20240233841
A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a…
NON-VOLATILE MEMORY WTH LOOP DEPENDANT RAMP-UP RATE
Granted: July 11, 2024
Application Number:
20240233826
A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to…
NONVOLATILE MEMORY WITH ONGOING PROGRAM READ
Granted: July 4, 2024
Application Number:
20240221803
An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory…
NAND PLANE BOUNDARY SHRINK
Granted: June 27, 2024
Application Number:
20240215240
Technology is disclosed herein for a memory device having a narrow gap between planes and a method of shrinking the gap between planes. A first and second adjacent planes each has a word line (WL) hookup region at mid-plane. A dummy array region resides between the two planes. The dummy array region may contain a stack of alternating layers of a first insulating material and a second insulating material. There is a first electrical isolation structure between the dummy array region and a…
NON-VOLATILE MEMORY WITH ERASE DEPTH DETECTION AND ADAPTIVE ADJUSTMENT TO PROGRAMMING
Granted: June 27, 2024
Application Number:
20240212768
A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.
MULTI-STAGE PROGRAMMING TECHNIQUES WITH THREE STATES PER MEMORY CELL PARITY
Granted: June 27, 2024
Application Number:
20240212767
The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes…
APPARATUS AND METHOD FOR DETECTING NEIGHBOR PLANE ERASE FAILURES
Granted: June 27, 2024
Application Number:
20240212764
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.
X-DIRECTION DIVIDED SUB-BLOCK MODE IN NAND
Granted: June 27, 2024
Application Number:
20240212755
A memory system is described having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its…
WORD LINE-DEPENDENT WORD LINE AND CHANNEL READ SETUP TIME IN FIRST READ STATE OF NON-VOLATILE MEMORY
Granted: June 27, 2024
Application Number:
20240212737
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a…
APPARATUS AND METHODS FOR SMART VERIFY WITH ADAPTIVE VOLTAGE OFFSET
Granted: June 20, 2024
Application Number:
20240203512
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an…
