PROGRAM TAIL PLANE COMPARATOR FOR NON-VOLATILE MEMORY STRUCTURES
Granted: November 10, 2022
Application Number:
20220359023
A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing…
MEMORY APPARATUS AND METHOD OF OPERATION USING ADAPTIVE ERASE TIME COMPENSATION FOR SEGMENTED ERASE
Granted: October 20, 2022
Application Number:
20220336029
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed…
MEMORY PROGRAMMING WITH SELECTIVELY SKIPPED BITSCANS AND FEWER VERIFY PULSES FOR PERFORMANCE IMPROVEMENT
Granted: October 20, 2022
Application Number:
20220336019
An apparatus that includes a word line with a plurality of memory cells that are able to be programmed to a plurality of data states is provided. The apparatus further includes a programming circuit. The programming circuit is configured to program the memory cells and count the number of verify pulses at a first verify voltage level that are performed during programming of the memory cells to a first programmed data state to determine a verify count. During programming to a second data…
FORCED CURRENT ACCESS WITH VOLTAGE CLAMPING IN CROSS-POINT ARRAY
Granted: October 20, 2022
Application Number:
20220335999
Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not…
FORCED CURRENT ACCESS WITH VOLTAGE CLAMPING IN CROSS-POINT ARRAY
Granted: October 20, 2022
Application Number:
20220335998
Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not…
MULTI-LEVEL PROGRAM PULSE FOR PROGRAMMING SINGLE LEVEL MEMORY CELLS TO REDUCE DAMAGE
Granted: October 13, 2022
Application Number:
20220328112
Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass…
MEMORY APPARATUS AND METHOD OF OPERATION USING STATE BIT-SCAN DEPENDENT RAMP RATE FOR PEAK CURRENT REDUCTION DURING PROGRAM OPERATION
Granted: October 6, 2022
Application Number:
20220319605
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the…
NON-VOLATILE MEMORY WITH DIFFERENT WORD LINE HOOK UP REGIONS BASED ON PASS THROUGH SIGNALS
Granted: October 6, 2022
Application Number:
20220319603
To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.
PREVENTION OF LATENT BLOCK FAILS IN THREE-DIMENSIONAL NAND
Granted: September 29, 2022
Application Number:
20220310161
Technology is disclosed for detecting latent defects in non-volatile storage systems. Prior to writing data, a stress voltage is applied to SGS transistors in a 3D memory structure. After applying the stress voltage, the Vt of the SGS transistors are tested to determine whether they meet a criterion. The criterion may be whether a Vt distribution of the SGS transistors falls within an allowed range. If the criterion is not met, then a sub-block mode may be enabled. In the sub-block mode,…
ERASE TAIL COMPARATOR SCHEME
Granted: September 29, 2022
Application Number:
20220310179
A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of…
Program With Consecutive Verifies For Non-Volatile Memory
Granted: September 22, 2022
Application Number:
20220301644
A data storage system includes a storage medium including a plurality of strings of single-level cell (SLC) memory cells connected to a plurality of word lines; and a storage controller in communication with the storage medium, the storage controller including write circuitry configured to write data to the storage medium by: selecting a first word line of the plurality of word lines, the first word line being connected to a first plurality of strings; consecutively programming a first…
Nonconsecutive Mapping Scheme for Data Path Circuitry in a Storage Device
Granted: September 22, 2022
Application Number:
20220300162
A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column…
REVERSE VT-STATE OPERATION AND OPTIMIZED BICS DEVICE STRUCTURE
Granted: September 15, 2022
Application Number:
20220293198
Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the…
COUNTERMEASURES FOR PERIODIC OVER PROGRAMMING FOR NON-VOLATILE MEMORY
Granted: September 15, 2022
Application Number:
20220293197
A non-volatile memory apparatus and method of operation are provided. The apparatus includes storage elements connected to a word line. Each of the storage elements is configured to be programmed to a respective target data state. The apparatus also includes a respective bit line associated with each of the storage elements and a control circuit configured to apply a plurality of program pulses to the word line that progressively increase by a program step voltage. The control circuit…
SIGNAL AMPLIFICATION IN MRAM DURING READING
Granted: September 15, 2022
Application Number:
20220293156
A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first…
APPLICATION BASED VERIFY LEVEL OFFSETS FOR NON-VOLATILE MEMORY
Granted: September 8, 2022
Application Number:
20220284971
A memory apparatus and method of operation are provided. The apparatus includes a plurality of memory cells. Each of the plurality of memory cells is connected to one of a plurality of word lines and is arranged in one of a plurality of blocks. Each of the plurality of memory cells is configured to retain a threshold voltage corresponding to one of a plurality of data states. A control circuit is coupled to the plurality of word lines and is configured to detect at least one use…
NEGATIVE BIT LINE BIASING DURING QUICK PASS WRITE PROGRAMMING
Granted: September 8, 2022
Application Number:
20220284965
A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled…
PEAK CURRENT AND PROGRAM TIME OPTIMIZATION THROUGH LOOP DEPENDENT VOLTAGE RAMP TARGET AND TIMING CONTROL
Granted: September 8, 2022
Application Number:
20220284964
An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a…
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
Granted: September 8, 2022
Application Number:
20220284961
The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is…
READ AND VERIFY METHODOLOGY AND STRUCTURE TO COUNTER GATE SiO2 DEPENDENCE OF NON VOLATILE MEMORY CELLS
Granted: May 12, 2022
Application Number:
20220148665
A method for programming a target memory cell in a memory array of a non-volatile memory system, the method comprising defining a default read biasing voltage value and a default verify biasing voltage value for each program state of a target memory cell of a memory structure, determining a location of a target memory cell within the memory structure and, based upon the determined location of the target memory cell, applying a first incremental offset voltage to the default read biasing…
