COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NAND MEMORY FOR NEURAL NETWORKS WITH WEIGHT AND INPUT LEVEL EXPANSIONS
Granted: December 15, 2022
Application Number:
20220398439
A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value,…
COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NOR MEMORY FOR NEURAL NETWORKS
Granted: December 15, 2022
Application Number:
20220398438
A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the…
SYSTEMS AND METHODS FOR DISTRIBUTING PROGRAMMING SPEED AMONG BLOCKS WITH DIFFERENT PROGRAM-ERASE CYCLE COUNTS
Granted: December 8, 2022
Application Number:
20220392556
Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the…
NONVOLATILE MEMORY WITH DATA RECOVERY
Granted: December 8, 2022
Application Number:
20220392555
An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data…
SYSTEMS AND METHODS FOR DETECTING ERRATIC PROGRAMMING IN A MEMORY SYSTEM
Granted: December 8, 2022
Application Number:
20220392553
The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line…
PEAK AND AVERAGE ICC REDUCTION BY TIER-BASED SENSING DURING PROGRAM VERIFY OPERATIONS OF NON-VOLATILE MEMORY STRUCTURES
Granted: December 8, 2022
Application Number:
20220392552
A method for programming a memory block of a non-volatile memory structure, wherein the method comprises, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.
TRIGGERING NEXT STATE VERIFY IN PROGRAM LOOP FOR NONVOLATILE MEMORY
Granted: December 8, 2022
Application Number:
20220392551
Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the…
EFFICIENT READ OF NAND WITH READ DISTURB MITIGATION
Granted: December 1, 2022
Application Number:
20220383961
Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells…
SYSTEM AND METHODS FOR PROGRAMMING NONVOLATILE MEMORY HAVING PARTIAL SELECT GATE DRAINS
Granted: December 1, 2022
Application Number:
20220383967
Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory…
NON-VOLATILE MEMORY WITH FAST MULTI-LEVEL PROGRAM VERIFY
Granted: December 1, 2022
Application Number:
20220383965
To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate…
NON-VOLATILE MEMORY WITH SPEED CONTROL
Granted: December 1, 2022
Application Number:
20220383956
A non-volatile memory system adjusts the speed of a memory operation for a subset of non-volatile memory cells. For example, during a GIDL based erase process, the GIDL generation can be dampened for a subset of memory cells (e.g., for a set of NAND strings, or one or more sub-blocks).
PERIODIC WRITE TO IMPROVE DATA RETENTION
Granted: November 24, 2022
Application Number:
20220375524
A nonvolatile memory control method includes a step of writing, repeatedly to a nonvolatile memory cells. The method continues with detecting when writing reaches a writing threshold value. Upon reaching the writing threshold, the method continues with driving a charge to at least one parasitic area intermediate at least two charge storage areas of the nonvolatile memory cells to improve data retention in at least one of the at least two charge storage areas of the nonvolatile memory…
MEMORY APPARATUS AND METHOD OF OPERATION USING NEGATIVE KICK CLAMP FOR FAST READ
Granted: November 24, 2022
Application Number:
20220375515
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a…
Aggressive Quick-Pass Multiphase Programming for Voltage Distribution State Separation in Non-Volatile Memory
Granted: November 24, 2022
Application Number:
20220375513
A multiphase programming scheme for programming a plurality of memory cells of a data storage system includes a first programming phase in which a first set of voltage distributions of the plurality of memory cells is programmed by applying a first plurality of program pulses to word lines of the plurality of memory cells, and a second programming phase in which a second set of voltage distributions is programmed by applying a second plurality of program pulses to the word lines of the…
READ OPERATION OR WORD LINE VOLTAGE REFRESH OPERATION IN MEMORY DEVICE WITH REDUCED PEAK CURRENT
Granted: November 17, 2022
Application Number:
20220366990
Apparatuses and techniques are described for reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different…
DROPOUT IN NEUTRAL NETWORKS USING THRESHOLD SWITCHING SELECTORS IN NON-VOLATILE MEMORIES
Granted: November 17, 2022
Application Number:
20220366211
A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors,…
ARCHITECTURE DESIGN FOR ENSEMBLE BINARY NEURAL NETWORK (EBNN) INFERENCE ENGINE ON SINGLE-LEVEL MEMORY CELL ARRAYS
Granted: November 10, 2022
Application Number:
20220358354
To improve efficiencies for inferencing operations of neural networks, ensemble neural networks are used for compute-in-memory inferencing. In an ensemble neural network, the layers of a neural network are replaced by an ensemble of multiple smaller neural network generated from subsets of the same training data as would be used for the layers of the full neural network. Although the individual smaller network layers are “weak classifiers” that will be less accurate than the full…
MODIFIED VERIFY IN A MEMORY DEVICE
Granted: November 10, 2022
Application Number:
20220359024
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line,…
NONVOLATILE MEMORY WITH EFFICIENT LOOK-AHEAD READ
Granted: November 10, 2022
Application Number:
20220359017
An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased…
NONVOLATILE MEMORY WITH COMBINED READS
Granted: November 10, 2022
Application Number:
20220358995
An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. Each non-volatile memory cell is configured to store a plurality of bits of a plurality of logical pages including at least a first bit of a first logical page, a second bit of a second logical page and a third bit of a third logical page. The control circuits are configured to select a subset of the plurality of logical pages for reading, perform pre-read steps, and read a first and…
