NON-VOLATILE MEMORY ARRAY LEAKAGE DETECTION
Granted: December 23, 2021
Application Number:
20210398602
An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage…
LEAKAGE REDUCTION CIRCUIT FOR READ-ONLY MEMORY (ROM) STRUCTURES
Granted: December 23, 2021
Application Number:
20210398594
A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage…
MULTI-PRECISION DIGITAL COMPUTE-IN-MEMORY DEEP NEURAL NETWORK ENGINE FOR FLEXIBLE AND ENERGY EFFICIENT INFERENCING
Granted: December 23, 2021
Application Number:
20210397974
Anon-volatile memory structure capable of storing weights for layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. An in-array multiplication can be performed between multi-bit valued inputs, or activations, for a layer of the DNN and multi-bit valued weights of the layer. Each bit of a weight value is stored in a binary valued memory cell of the memory array and each bit of the input is applied as a binary input to a word line of…
RECURRENT NEURAL NETWORK INFERENCE ENGINE WITH GATED RECURRENT UNIT CELL AND NON-VOLATILE MEMORY ARRAYS
Granted: December 23, 2021
Application Number:
20210397931
A non-volatile memory device includes arrays of non-volatile memory cells that are configured to the store weights for a recurrent neural network (RNN) inference engine with a gated recurrent unit (GRU) cell. A set three non-volatile memory arrays, such as formed of storage class memory, store a corresponding three sets of weights and are used to perform compute-in-memory inferencing. The hidden state of a previous iteration and an external input are applied to the weights of the first…
SYSTEM IDLE TIME REDUCTION METHODS AND APPARATUS
Granted: December 23, 2021
Application Number:
20210397372
An apparatus is provided that includes a memory die including a pipeline circuit coupled to a memory structure. The memory die is configured to execute a first command by receiving in the pipeline circuit data to be written to the memory structure, processing the received data in the pipeline circuit and providing the processed data to the memory structure, predicting that the pipeline circuit has completed processing the received data, and ending execution of the first command based on…
IMPLEMENTATION OF DEEP NEURAL NETWORKS FOR TESTING AND QUALITY CONTROL IN THE PRODUCTION OF MEMORY DEVICES
Granted: December 23, 2021
Application Number:
20210397170
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
APPARATUS, SYSTEM, AND METHOD FOR TRIMMING ANALOG TEMPERATURE SENSORS
Granted: December 23, 2021
Application Number:
20210396604
A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine…
PLANE PROGRAMMING SCHEME FOR NON-VOLATILE MEMORY WITH LARGE BLOCK SIZES
Granted: December 16, 2021
Application Number:
20210389879
For a non-volatile memory system with a multi-plane memory die having a large block size, to be able to more readily accommodate zone-based host data using zones that are of a smaller size that the block size on the memory, the memory system assigns data from different zones to different subsets of the planes of a common memory die. The memory system is configured to accumulate the data from the different zones into different write queues and then assemble the data from the different…
CHARGE PUMP WITH WIDE CURRENT RANGE
Granted: December 16, 2021
Application Number:
20210391865
A charge pump has a first branch that includes a first node connected between a first pull-up switch and a first pull-down switch and a second branch that includes a second node connected between a second pull-up switch and a second pull-down switch. The second branch is connected in parallel with the first branch. The charge pump has a voltage equalization circuit to equalize a first voltage at the first node and a second voltage at the second node. A third branch includes a third node…
NEIGHBOR AWARE MULTI-BIAS PROGRAMMING IN SCALED BICS
Granted: December 16, 2021
Application Number:
20210391012
A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N?1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to…
ECC IN INTEGRATED MEMORY ASSEMBLY
Granted: December 9, 2021
Application Number:
20210383886
Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory…
COUPLING CAPACITANCE REDUCTION DURING PROGRAM VERIFY FOR PERFORMANCE IMPROVEMENT
Granted: December 9, 2021
Application Number:
20210383879
A memory apparatus and method of operation is provided. The apparatus includes selected memory cells coupled to a selected word line and each storing a threshold voltage representative of a selected cell data programmed in a program-verify operation. Unselected memory cells are coupled to a neighbor word line disposed adjacent the selected word line. A control circuit is coupled to the selected and unselected memory cells and configured to ramp from at least one initial voltage applied…
PROGRAMMING OF MEMORY CELLS USING A MEMORY STRING DEPENDENT PROGRAM VOLTAGE
Granted: December 9, 2021
Application Number:
20210383870
A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array…
CIRCUIT FOR DETECTING PIN-TO-PIN LEAKS OF AN INTEGRATED CIRCUIT PACKAGE
Granted: December 2, 2021
Application Number:
20210373085
Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path…
CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES
Granted: November 18, 2021
Application Number:
20210358553
Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to…
OVERWRITE READ METHODS FOR RESISTANCE SWITCHING MEMORY DEVICES
Granted: November 4, 2021
Application Number:
20210343338
A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.
VERTICAL MAPPING AND COMPUTING FOR DEEP NEURAL NETWORKS IN NON-VOLATILE MEMORY
Granted: November 4, 2021
Application Number:
20210342676
Anon-volatile memory structure capable of storing layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. A stack of bonded die pairs is connected by through silicon vias. Each bonded die pair includes a memory die, having one or more memory arrays onto which layers of the neural network are mapped, and a peripheral circuitry die, including the control circuits for performing the convolution or multiplication for the bonded die pair.…
VERTICAL MAPPING AND COMPUTING FOR DEEP NEURAL NETWORKS IN NON-VOLATILE MEMORY
Granted: November 4, 2021
Application Number:
20210342671
A non-volatile memory structure capable of storing layers of a deep neural network (DNN) and perform an inferencing operation within the structure is presented. A stack of bonded die pairs is connected by through silicon vias. Each bonded die pair includes a memory die, having one or more memory arrays onto which layers of the neural network are mapped, and a peripheral circuitry die, including the control circuits for performing the convolution or multiplication for the bonded die pair.…
RECONFIGURABLE INPUT PRECISION IN-MEMORY COMPUTING
Granted: October 21, 2021
Application Number:
20210326110
Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node…
NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP
Granted: October 21, 2021
Application Number:
20210327518
A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks…
