RECONFIGURABLE INPUT PRECISION IN-MEMORY COMPUTING
Granted: October 21, 2021
Application Number:
20210326110
Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node…
APPARATUS AND METHODS FOR QUARTER BIT LINE SENSING
Granted: October 14, 2021
Application Number:
20210319833
An apparatus is provided that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals.
COLUMN REDUNDANCY DATA ARCHITECTURE FOR YIELD IMPROVEMENT
Granted: October 14, 2021
Application Number:
20210318939
Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the…
ONE SELECTOR ONE RESISTOR MRAM CROSSPOINT MEMORY ARRAY FABRICATION METHODS
Granted: October 7, 2021
Application Number:
20210313392
A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F2 and 4F2.
INPUT/OUTPUT CIRCUIT INTERNAL LOOPBACK
Granted: September 30, 2021
Application Number:
20210304834
Technology is disclosed herein for a semiconductor die, and controlling operation of the semiconductor die. In some aspects, a semiconductor die is configured to test an I/O circuit on the semiconductor die. The semiconductor die has an input circuit that compares a voltage signal at one of a first input or a second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The first input may be connected to an I/O contact.…
PEAK AND AVERAGE CURRENT REDUCTION FOR SUB BLOCK MEMORY OPERATION
Granted: September 30, 2021
Application Number:
20210304822
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The…
PHYSICAL UNCLONABLE FUNCTION (PUF) FOR NAND OPERATOR
Granted: September 30, 2021
Application Number:
20210303182
Apparatus and methods implement a physical unclonable function (PUF) from NAND operations. A NAND flash memory device may generate an unclonable natural random sequence of bits based on a threshold voltage of a plurality of cells in a memory cell array. The unclonable natural random sequence may be stored starting at an address of the memory cell array. A selected subsequence of the unclonable natural random sequence may be stored in a first set of data latches, and target data may be…
CIRCUITS AND METHODS FOR RELIABLE REPLACEMENT OF BAD COLUMNS IN A MEMORY DEVICE
Granted: September 23, 2021
Application Number:
20210295945
An apparatus includes nonvolatile memory cells arranged in columns including a plurality of redundant columns with control circuits coupled to the nonvolatile memory cells. The control circuits are configured to maintain an ordered list of bad columns replaced by redundant columns. The control circuits are configured to detect an out-of-order entry in the ordered list of bad columns replaced by redundant columns.
PRE-COMPUTATION OF MEMORY CORE CONTROL SIGNALS
Granted: September 9, 2021
Application Number:
20210279169
An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the…
SEMICONDUCTOR DEVICE INCLUDING FRACTURED SEMICONDUCTOR DIES
Granted: September 9, 2021
Application Number:
20210280559
A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the…
PRE-COMPUTATION OF MEMORY CORE CONTROL SIGNALS
Granted: September 9, 2021
Application Number:
20210279168
An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the…
DETECTION OF A LAST PROGRAMMING LOOP FOR SYSTEM PERFORMANCE GAIN
Granted: September 2, 2021
Application Number:
20210272639
A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further…
SOURCE SIDE PRECHARGE AND BOOSTING IMPROVEMENT FOR REVERSE ORDER PROGRAM
Granted: August 26, 2021
Application Number:
20210264964
This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a…
REFRESH OPERATIONS FOR MEMORY CELLS BASED ON SUSCEPTIBILITY TO READ ERRORS
Granted: August 19, 2021
Application Number:
20210257039
Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high…
SYSTEMS AND METHODS FOR PROGRAM VERIFICATION ON A MEMORY SYSTEM
Granted: August 19, 2021
Application Number:
20210257037
A method for memory program verification includes performing a write operation on memory cells of a memory device. The method also includes identifying memory strings associated with respective memory cells of the memory cells. The method also includes identifying a first memory string of the memory strings. The method also includes disabling a portion of a write verification for the first memory string. The method also includes enabling the portion of the write verification for other…
MEMORY SCALING SEMICONDUCTOR DEVICE
Granted: August 12, 2021
Application Number:
20210249385
A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to…
ONE SELECTOR ONE RESISTOR RAM THRESHOLD VOLTAGE DRIFT AND OFFSET VOLTAGE COMPENSATION METHODS
Granted: August 12, 2021
Application Number:
20210249073
An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is…
CONTROLLING TIMING AND RAMP RATE OF PROGRAM-INHIBIT VOLTAGE SIGNAL DURING PROGRAMMING TO OPTIMIZE PEAK CURRENT
Granted: August 5, 2021
Application Number:
20210241836
Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with…
CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES
Granted: July 29, 2021
Application Number:
20210233589
Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first…
IN-STORAGE LOGIC FOR HARDWARE ACCELERATORS
Granted: July 29, 2021
Application Number:
20210233592
Systems and methods for performing in-storage logic operations using one or more memory cell transistors and a programmable sense amplifier are described. The logic operations may comprise basic Boolean logic operations (e.g., OR and AND operations) or secondary Boolean logic operations (e.g., XOR and IMP operations). The one or more memory cell transistors may be used for storing user data during a first time period and then used for performing a logic operation during a second time…
