MODIFIED VERIFY SCHEME FOR PROGRAMMING A MEMORY APPARATUS
Granted: July 1, 2021
Application Number:
20210202022
A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory…
A SYSTEM AND METHOD OF READING TWO PAGES IN A NONVOLATILE MEMORY
Granted: July 1, 2021
Application Number:
20210202011
Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate…
KERNEL TRANSFORMATION TECHNIQUES TO REDUCE POWER CONSUMPTION OF BINARY INPUT, BINARY WEIGHT IN-MEMORY CONVOLUTIONAL NEURAL NETWORK INFERENCE ENGINE
Granted: June 24, 2021
Application Number:
20210192325
Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero…
CENTRALIZED FIXED RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT IN NON-VOLATILE MEMORY
Granted: June 24, 2021
Application Number:
20210193226
In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up…
SENSE AMPLIFIER FOR BIDIRECTIONAL SENSING OF MEMORY CELLS OF A NON-VOLATILE MEMORY
Granted: June 24, 2021
Application Number:
20210193230
A sense amplifier for a memory circuit is presented that can sense a selected memory cell in either a first sensing mode, in which current from the selected memory cell flows from the memory cells into the sense amplifier, or a second sensing mode, in which current is discharged from the sense amplifier through the selected memory cell. In the first sensing mode, current from a selected memory cell is conducted through cascaded PMOS transistors to charge a sensing node, with the…
VOLTAGE GENERATION SYSTEM AND METHOD FOR NEGATIVE AND POSITIVE VOLTAGE DRIVEN SYSTEMS
Granted: June 17, 2021
Application Number:
20210181777
Apparatuses and techniques are described for providing a positive voltage source and a negative voltage source in a circuit. The positive voltage source and the negative voltage source have a common ground node. The positive voltage source can be provided using a current mirror in which a current in a first path is copied to provide a current in a second path. The currents of the first and second paths are sunk at the common ground node. The negative voltage source can be provided using…
CROSSPOINT MEMORY ARCHITECTURE FOR HIGH BANDWIDTH OPERATION WITH SMALL PAGE BUFFER
Granted: June 17, 2021
Application Number:
20210181979
Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address…
PIPELINED MICRO CONTROLLER UNIT
Granted: June 17, 2021
Application Number:
20210182178
A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
ERASE SUSPEND SCHEME IN A STORAGE DEVICE
Granted: June 17, 2021
Application Number:
20210183450
A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the…
NON-VOLATILE MEMORY WITH ERASE VERIFY SKIP
Granted: June 10, 2021
Application Number:
20210174887
A non-volatile storage apparatus is configured to perform erase verify during an erase process in order to account for differences in erase speed. In order to reduce the time used to perform the erase process (which includes the erase verify), the erase verify operation is skipped for certain memory cells based on a system parameter. For example, when erasing a block of memory cells, a series of erase voltage pulses are applied to the NAND strings in outer sub-blocks and inner sub-blocks…
TEMPERATURE AND CYCLING DEPENDENT REFRESH OPERATION FOR MEMORY CELLS
Granted: June 10, 2021
Application Number:
20210174886
Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be…
BOOSTING READ SCHEME WITH BACK-GATE BIAS
Granted: June 10, 2021
Application Number:
20210174881
Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the…
BLOCK QUALITY CLASSIFICATION AT TESTING FOR NON-VOLATILE MEMORY, AND MULTIPLE BAD BLOCK FLAGS FOR PRODUCT DIVERSITY
Granted: June 10, 2021
Application Number:
20210173734
For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test…
SYSTEMS AND METHODS FOR DEFINING MEMORY SUB-BLOCKS
Granted: June 10, 2021
Application Number:
20210173559
A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes…
DYNAMIC RE-EVALUATION OF PARAMETERS FOR NON-VOLATILE MEMORY USING MICROCONTROLLER
Granted: May 27, 2021
Application Number:
20210157607
A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of…
DIFFERENTIAL DBUS SCHEME FOR LOW-LATENCY RANDOM READ FOR NAND MEMORIES
Granted: May 13, 2021
Application Number:
20210142858
A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.
DOUBLE WRITE/READ THROUGHPUT BY CAA NAND
Granted: May 13, 2021
Application Number:
20210142841
A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions…
BI-DIRECTIONAL SENSING IN A MEMORY
Granted: May 6, 2021
Application Number:
20210134372
A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include…
METHOD OF CONCURRENT MULTI-STATE PROGRAMMING OF NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP
Granted: May 6, 2021
Application Number:
20210134370
A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods…
METHOD FOR CONCURRENT PROGRAMMING
Granted: May 6, 2021
Application Number:
20210134369
A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods…
