TEMPERATURE DEPENDENT PROGRAMMING TECHNIQUES IN A MEMORY DEVICE
Granted: November 30, 2023
Application Number:
20230386586
The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a…
NON-VOLATILE MEMORY WITH ENGINEERED CHANNEL GRADIENT
Granted: November 30, 2023
Application Number:
20230386585
To save power during a read process, NAND strings of each sub-block of a block have independently controlled source side select lines connected to source side select gates and drain side select lines connected to drain side select gates so that NAND strings of unselected sub-blocks can float and not draw current. To prevent read disturb in NAND strings of unselected sub-blocks, after all word lines are raised to a pass gate voltage, unselected word lines nearby the selected word line are…
METHOD TO OPTIMIZE FIRST READ VERSUS SECOND READ MARGIN BY SWITCHING BOOST TIMING
Granted: November 30, 2023
Application Number:
20230386580
An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.
PUMP SKIP FOR FAST SINGLE-LEVEL CELL NON-VOLATILE MEMORY
Granted: November 23, 2023
Application Number:
20230377657
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to…
TECHNIQUES FOR READING MEMORY CELLS IN A MEMORY DEVICE DURING A MULTI-PASS PROGRAMMING OPERATION
Granted: November 23, 2023
Application Number:
20230377655
The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine…
MULTI-PASS PROGRAMMING OPERATION SEQUENCE IN A MEMORY DEVICE
Granted: November 23, 2023
Application Number:
20230377643
A controller is configured to program the memory cells to a first set of data states in a first programming pass and to a greater second set of data states in a second programming pass. The controller performs the first programming pass on the first word line. The controller then repeats the process of programming a portion of another word line and then comparing an upper tail of an erased data state of the first word line to a critical voltage until the upper tail of the erased data…
CHARGE PUMP CURRENT REGULATION DURING VOLTAGE RAMP
Granted: November 16, 2023
Application Number:
20230368847
Technology is disclosed herein for a memory system that regulates charge pump current during a ramp up of the output voltage. The memory systems operates the charge pump in a current regulation mode while the charge pump output voltage ramps up. After the output voltage crosses a threshold voltage, the charge pump is operated in a voltage regulation mode in which the output voltage is regulated to a target output voltage. In one aspect, the memory system generates a random duty cycle…
NON-VOLATILE MEMORY WITH ISOLATION LATCH SHARED BETWEEN DATA LATCH GROUPS
Granted: November 16, 2023
Application Number:
20230368852
A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device…
POST-WRITE READ TECHNIQUES TO IMPROVE PROGRAMMING RELIABILITY IN A MEMORY DEVICE
Granted: November 16, 2023
Application Number:
20230368851
The memory device includes a controller that is configured to program a plurality of memory cells of a selected word line in a plurality of programming loops and count the number of programming loops to complete programming. The controller is also configured to compare the number of programming loops to complete programming of the memory cells of the selected word line to at least one of a predetermined upper limit and a predetermined lower limit to determine if a plane containing the…
SMART EARLY DETECTION OF WORDLINE-MEMORY HOLE DEFECTS WITH WORDLINE-DEPENDENT DUAL SENSING DURING ERASE VERIFY
Granted: November 16, 2023
Application Number:
20230368850
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block…
MEMORY CELL GROUP READ WITH COMPENSATION FOR DIFFERENT PROGRAMMING SPEEDS
Granted: November 16, 2023
Application Number:
20230368846
Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the…
PRE-READ CYCLE TIMING SHRINK BY SGD BIAS CONTROL AND PAGE AND WORDLINE CONTROL
Granted: November 16, 2023
Application Number:
20230368844
A method of operating a non-volatile semiconductor memory device is disclosed. The method comprises: during a first pre-read cycle of a read operation, ramping up a control signal on a wordline selected for the read operation to a first target pre-read voltage and ramping up a control signal on a drain-side select (SGD) transistor of an unselected string of the plurality of strings to a second target pre-read voltage. The method further comprises during a second pre-read cycle of the…
CIRCUITRY ARRANGEMENT IN A FLOORPLAN OF A MEMORY DEVICE
Granted: November 16, 2023
Application Number:
20230367944
The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of…
TIME-TAGGING READ LEVELS OF MULTIPLE WORDLINES FOR OPEN BLOCK DATA RETENTION
Granted: November 2, 2023
Application Number:
20230352108
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold…
FAST OPEN BLOCK ERASE IN NON-VOLATILE MEMORY STRUCTURES
Granted: November 2, 2023
Application Number:
20230352097
A method for performing an erase operation of a partially programmed memory block of a non-volatile memory structure. The method comprises: (1) applying an erase voltage bias level to a channel region of the memory block, (2) applying a word line voltage level to all programmed word line(s) of the memory block, (3) applying a “float” condition to all unprogrammed word line(s) of the memory block, and (4) applying an erase verify operation to all word line(s) of the memory block,…
TWO-SIDE STAIRCASE PRE-CHARGE IN SUB-BLOCK MODE OF THREE-TIER NON-VOLATILE MEMORY ARCHITECTURE
Granted: October 26, 2023
Application Number:
20230343400
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word…
IR DROP COMPENSATION FOR SENSING MEMORY
Granted: October 26, 2023
Application Number:
20230343385
Technology is disclosed herein for sensing memory cells while compensating for resistance along an electrical pathway between a voltage driver and a control line connected to the memory cells. A control circuit provides a voltage from the voltage driver over a first electrical pathway to a control line in a first block and a second electrical pathway to a control line in a second block. The control circuit senses first memory cells in the first block and the second memory cells in the…
FIRST FIRE AND COLD START IN MEMORIES WITH THRESHOLD SWITCHING SELECTORS
Granted: October 12, 2023
Application Number:
20230326506
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory…
DYNAMIC SENSE AMPLIFIER SUPPLY VOLTAGE FOR POWER AND DIE SIZE REDUCTION
Granted: October 12, 2023
Application Number:
20230326531
Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells…
MEMORY APPARATUS AND METHOD OF OPERATION USING STATE DEPENDENT STROBE TIER SCAN TO REDUCE PEAK ICC
Granted: October 12, 2023
Application Number:
20230326530
A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes…
