UTILIZING DATA PATTERN EFFECT TO CONTROL READ CLOCK TIMING AND BIT LINE KICK FOR READ TIME REDUCTION
Granted: October 5, 2023
Application Number:
20230317174
A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to…
PROGRAMMING TECHNIQUES TO REDUCE PROGRAMMING STRESS IN A MEMORY DEVICE
Granted: October 5, 2023
Application Number:
20230317170
The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the…
NON-VOLATILE MEMORY WITH ZONED CONTROL OF PROGRAMMING
Granted: October 5, 2023
Application Number:
20230317169
A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a…
QUICK PASS WRITE PROGRAMMING TECHNIQUES IN A MEMORY DEVICE
Granted: September 28, 2023
Application Number:
20230307072
The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count…
VERIFY TECHNIQUES FOR CURRENT REDUCTION IN A MEMORY DEVICE
Granted: September 28, 2023
Application Number:
20230307071
The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first…
RECOVERY PULSES TO COUNTER CUMULATIVE READ DISTURB
Granted: September 28, 2023
Application Number:
20230307070
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift…
VARIABLE BIT LINE BIAS FOR NONVOLATILE MEMORY
Granted: September 21, 2023
Application Number:
20230298667
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a…
NON-VOLATILE MEMORY WITH UPDATING OF READ COMPARE VOLTAGES BASED ON MEASURED CURRENT
Granted: September 21, 2023
Application Number:
20230298678
A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
VARIABLE BIT LINE BIAS FOR NONVOLATILE MEMORY
Granted: September 21, 2023
Application Number:
20230298667
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a…
NON-VOLATILE MEMORY WITH UPDATING OF READ COMPARE VOLTAGES BASED ON MEASURED CURRENT
Granted: September 21, 2023
Application Number:
20230298678
A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.
MLC PROGRAMMING TECHNIQUES IN A MEMORY DEVICE
Granted: September 14, 2023
Application Number:
20230290419
The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the…
LOW POWER MODE WITH READ SEQUENCE ADJUSTMENT
Granted: September 14, 2023
Application Number:
20230290403
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order…
EP CYCLING DEPENDENT ASYMMETRIC/SYMMETRIC VPASS CONVERSION IN NON-VOLATILE MEMORY STRUCTURES
Granted: September 7, 2023
Application Number:
20230282295
A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprises determining a total number of erase/programming (EP) cycles that were applied previously to the memory cell and, (1) if the determined total number of cycles does not exceed a threshold value, applying an asymmetric programming scheme, and, (2) if the determined total number of cycles exceeds the threshold value, applying a symmetric programming scheme. Further, a…
LOW POWER READ METHOD AND A MEMORY DEVICE CAPABLE THEREOF
Granted: September 7, 2023
Application Number:
20230282288
The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read…
SELECTIVE INHIBIT BITLINE VOLTAGE TO CELLS WITH WORSE PROGRAM DISTURB
Granted: August 31, 2023
Application Number:
20230274785
A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage…
SELF-DIAGNOSTIC SMART VERIFY ALGORITHM IN USER MODE TO PREVENT UNRELIABLE ACQUIRED SMART VERIFY PROGRAM VOLTAGE
Granted: August 24, 2023
Application Number:
20230268015
A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings. A control means is coupled to the word lines and the memory holes and programs the memory cells associated with a first one of the strings in a program operation and acquire a smart verify programming voltage in a smart verify operation…
NON-VOLATILE MEMORY WITH PLANE INDEPENDENT SCREENING
Granted: August 24, 2023
Application Number:
20230268013
A non-volatile storage apparatus that comprises a plurality of planes of non-volatile memory cells is capable of concurrently programming memory cells in multiple planes. In order to screen for failure of the programming process in a subset of planes, the completion of programming of a fastest plane to a particular data state is used as a trigger to test for program failure of other planes to a different data state. In one embodiment, the test for program failure of other planes to the…
NON-VOLATILE MEMORY WITH EFFICIENT WORD LINE HOOK-UP
Granted: August 24, 2023
Application Number:
20230268001
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile…
CROSS-POINT ARRAY IHOLD READ MARGIN IMPROVEMENT
Granted: August 24, 2023
Application Number:
20230267981
Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive…
CURRENT MIRROR CIRCUITS
Granted: August 17, 2023
Application Number:
20230259149
A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output…
