Semiconductor wafer configured for single touch-down testing
Granted: April 8, 2025
Patent Number:
12270853
A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
Access-controlled delivery of content to network attached storage
Granted: April 8, 2025
Patent Number:
12273330
A network attached storage device coupled to a local network and including a network interface configured to receive digital content from a remote content provider outside the local network. The network attached storage device includes storage having a first region accessible by a user of the local network and a secure region. The network attached storage device includes a processor coupled to the storage, the processor configured to control access to the secure region of the storage…
Semiconductor device including through-package debug features
Granted: April 8, 2025
Patent Number:
12272609
A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor…
Vera detection method to catch erase fail
Granted: April 8, 2025
Patent Number:
12272417
Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a…
Reverse garbage collection process for a storage device
Granted: April 8, 2025
Patent Number:
12271617
A memory device includes a number of different memory dies and/or planes. One or more host operations, such as write operations and/or read operations, are performed on each memory die and/or plane in sequence. For example, from memory die 0 to memory die n. A garbage collection process is performed in parallel with the host operations. However, the garbage collection process is performed in a reverse order when compared with the order of the host operations. For example, the garbage…
Peer storage device messaging for vulnerability management
Granted: April 8, 2025
Patent Number:
12271486
Systems and methods for peer data storage device messaging over a peer channel, such as a control bus, for vulnerability management are disclosed. Storage devices may include a host interface configured to connect to a host system and a peer interface to establish peer communication independent of host availability. The storage devices may determine security issues (for themselves or for peer storage devices) and send a threat notification through the peer interface, enabling peer…
Providing host with multiple mapping information that span across multiple HPB regions
Granted: April 8, 2025
Patent Number:
12271301
A storage device minimizes HPB entry inactivation resulting from data associated with hot reads being retrieved from multiple HPB sub-regions covering a logical-to-physical table. The storage device may support the HPB feature and a multiple HPB sub-region mode. The storage device includes a controller that tracks a hit count associated with a logical block address in a read command. The controller determines that the hit count has reached a hit threshold and updates a hit table to…
Data storage device and method for performing an action on an area of memory to satisfy a host-provided target operating condition
Granted: April 8, 2025
Patent Number:
12271300
A data storage device and method are provided for performing an action on an area of memory to satisfy a host-provided target operating condition. In one embodiment, a controller of the data storage device is configured to: receive, from a host, an identification of an area of the memory and a target operating condition for the area of the memory; monitor the area of the memory to determine whether the area of the memory satisfies the target operating condition; and in response to…
Data storage device and method for host-assisted improved error recovery using a correlation factor
Granted: April 8, 2025
Patent Number:
12271261
A data storage device and method for host-assisted improved error recovery using a correlation factor are provided. In one embodiment, the data storage device receives, from a host, an indication that data associated with a first logical address is correlated with data associated with a second logical address; determines a correlation factor based on a degree of correlation between the data associated with the first logical address and the data associated with the second logical address;…
Current reference circuit with process, voltage, and wide-range temperature compensation
Granted: April 8, 2025
Patent Number:
12271217
Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on…
Three-dimensional memory device including discrete charge storage elements and methods of forming the same
Granted: April 1, 2025
Patent Number:
12267998
A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film. The memory film includes a contoured blocking dielectric layer including sac-shaped lateral protrusions located at levels of the electrically conductive layers, a…
Wireless device loss prevention and discovery
Granted: April 1, 2025
Patent Number:
12267775
A data storage device comprises a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, an energy harvesting component configured to produce electrical energy from an ambient energy source, and a beacon component, configured to wirelessly transmit a signal. The beacon component is configured to consume the electrical energy to wirelessly transmit the signal. The data storage device…
Reordering commands to optimize execution of the commands
Granted: April 1, 2025
Patent Number:
12265738
Optimizing the time that a link is active in a data storage device is desirable. Changing the way the device processes commands will minimize the link uptime and maximize the time that the link can remain in a low power mode. The data storage device will control the command arbitration from the host to aggregate together command chunks as large as possible, such that will extend the link down durations, and won't need to wake the link up occasionally. In another approach the execution of…
Segregating large data blocks for data storage system
Granted: April 1, 2025
Patent Number:
12265733
Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better…
Accelerated encryption during power loss
Granted: April 1, 2025
Patent Number:
12265478
The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of…
Dynamically determining a memory block threshold for initiating a garbage collection process
Granted: March 25, 2025
Patent Number:
12260085
A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are…
Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings
Granted: March 25, 2025
Patent Number:
12261080
A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a…
Data integrity check in non-volatile storage
Granted: March 25, 2025
Patent Number:
12260925
Technology is disclosed herein for checking data integrity in a non-volatile storage system. The storage system may operate in a first mode in which a data integrity check is performed in closed blocks until more than an allowed number of word lines fail the data integrity check. After a closed block has more than the allowed number of the word lines fail the data integrity check, then the storage system may operate in a second mode in which a data integrity check is performed in open…
Sense amplifier architecture providing reduced program verification time
Granted: March 25, 2025
Patent Number:
12260921
Systems and methods are provided for sensing a data state of a memory cell. In an example implementation, systems and methods disclosed herein perform a method that includes connecting a first sensing node and a second sensing node to a bitline of a sensing amplifier to simultaneously discharge first and second capacitors connected to the first and second sensing nodes, respectively, through the memory cell. After a first sensing period, the second sensing node is disconnected from the…
Commands splitting based on flat logical block address and security key
Granted: March 25, 2025
Patent Number:
12260131
Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion…
