Non-volatile memory with layout adaptive problematic word line detection
Granted: May 6, 2025
Patent Number:
12293800
In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global…
Apparatus and methods for smart verify with adaptive voltage offset
Granted: May 6, 2025
Patent Number:
12293797
An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an…
Storage system and method for implementation of symmetric tree models for read threshold calibration
Granted: May 6, 2025
Patent Number:
12293796
A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality…
Memory device with reinforcement learning with Q-learning acceleration
Granted: May 6, 2025
Patent Number:
12293109
The present disclosure generally relates to data storage devices, such as solid state drives. A data storage device includes a controller, one or more volatile memory locations, and one or more non-volatile memory locations. Computations, including reinforcement learning algorithms, may be completed by the controller using the one or more non-volatile memory locations. Data associated with reinforcement learning is stored in a table on one or more planes of the non-volatile memory, where…
Data storage device and method for improving asynchronous independent plane read (AIPR) utilization
Granted: May 6, 2025
Patent Number:
12293085
Some data storage devices have a plurality of memory dies that can be read in parallel for certain types of read requests. Read requests pertaining to a garbage collection operation are often generated sequentially and, thus, are not eligible for parallel execution in the memory dies. In an example data storage device presented herein, such read requests are consolidated and sent to the memory for execution in parallel across the memory dies.
Data storage device and method for performance-dependent storage of parity information
Granted: May 6, 2025
Patent Number:
12292796
A data storage device can store data and parity information for the data in its memory. In some storage methodologies, data and parity information are striped across a plurality of memory dies (e.g., in a redundant array of independent drives (RAID) configuration). That way, if one of the memory dies fails, the data or the parity information can be reconstructed from the other memory dies. These embodiments recognize that because parity information is used relatively infrequently, the…
Three-dimensional memory device containing deformation resistant trench fill structure and methods of making the same
Granted: April 29, 2025
Patent Number:
12288755
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner…
Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof
Granted: April 29, 2025
Patent Number:
12289889
A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding…
Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making the same
Granted: April 29, 2025
Patent Number:
12289887
A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film includes a resonant tunneling barrier stack, a barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the barrier layer. The barrier…
Multi-tier memory device with rounded joint structures and methods of making the same
Granted: April 29, 2025
Patent Number:
12289886
A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to…
Semiconductor device manufacturing process including forming a bonded assembly and substrate recycling
Granted: April 29, 2025
Patent Number:
12288719
A method includes forming an etch stop material layer and a planar sacrificial spacer layer over a front surface of a first substrate, forming an insulating encapsulation layer over the planar sacrificial spacer layer and on a backside surface and a side surface of the first substrate, forming a continuous structure including first semiconductor devices over a top surface of the insulating encapsulation layer, etching inter-die trenches within the continuous structure to divide the…
Non-volatile memory with sub-planes having individually biasable source lines
Granted: April 29, 2025
Patent Number:
12288586
To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.
Housings for electronic devices and memory devices
Granted: April 29, 2025
Patent Number:
12288573
Embodiments of the present disclosure generally relate to housings for, e.g., memory devices and electronic devices, and to processes for forming such housings. In an embodiment, an article for housing at least a portion of an electronic device is provided. The article includes a first component comprising a thermoplastic and a biodegradable filler or polymer, and a second component disposed on at least a portion of the first component, the second component comprising a plurality of…
Adaptive single-side erase to improve cell reliability
Granted: April 29, 2025
Patent Number:
12287974
A memory device includes control circuitry configured to perform an erase operation to erase memory cells of a memory block and perform an erase verify operation to verify whether the memory cells were sufficiently erased. To perform the erase operation, the control circuitry is configured to supply a first erase voltage pulse, perform the erase verify operation subsequent to supplying the first erase voltage pulse, subsequent to the erase verify operation, supply a first bias voltage to…
Wafer surface chemical distribution sensing system and methods for operating the same
Granted: April 29, 2025
Patent Number:
12285837
A method includes performing a chemical mechanical polishing (CMP) process on a wafer in a CMP apparatus, loading the wafer into a roll cleaning apparatus after performing the CMP process on the wafer, applying a fluid on a surface of the wafer; brushing the surface of the wafer with a rotating roll brush, and measuring a distribution of the fluid on the surface of the wafer while brushing the surface of the wafer.
Data storage device and method for performing an action on an area of memory to satisfy a host-provided target operating condition
Granted: April 8, 2025
Patent Number:
12271300
A data storage device and method are provided for performing an action on an area of memory to satisfy a host-provided target operating condition. In one embodiment, a controller of the data storage device is configured to: receive, from a host, an identification of an area of the memory and a target operating condition for the area of the memory; monitor the area of the memory to determine whether the area of the memory satisfies the target operating condition; and in response to…
Access-controlled delivery of content to network attached storage
Granted: April 8, 2025
Patent Number:
12273330
A network attached storage device coupled to a local network and including a network interface configured to receive digital content from a remote content provider outside the local network. The network attached storage device includes storage having a first region accessible by a user of the local network and a secure region. The network attached storage device includes a processor coupled to the storage, the processor configured to control access to the secure region of the storage…
Semiconductor device including through-package debug features
Granted: April 8, 2025
Patent Number:
12272609
A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor…
Vera detection method to catch erase fail
Granted: April 8, 2025
Patent Number:
12272417
Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a…
Reverse garbage collection process for a storage device
Granted: April 8, 2025
Patent Number:
12271617
A memory device includes a number of different memory dies and/or planes. One or more host operations, such as write operations and/or read operations, are performed on each memory die and/or plane in sequence. For example, from memory die 0 to memory die n. A garbage collection process is performed in parallel with the host operations. However, the garbage collection process is performed in a reverse order when compared with the order of the host operations. For example, the garbage…
