Dynamic and shared CMB and HMB allocation
Granted: April 22, 2025
Patent Number:
12282657
A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By…
Data storage device and method for time-pooled hot data relocation
Granted: April 22, 2025
Patent Number:
12282663
Post-write data management operations, such as refresh read, data scrub, and data relocation, are typically performed after a certain period of time has elapsed. However, performing such operations based on probability of access can provide advantages. So, in one example, a post-write data management operation is performed more frequently on relatively-warmer data than on relatively-colder data.
Array dependent voltage compensation in a memory device
Granted: April 22, 2025
Patent Number:
12283324
The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the…
Multiple stage fuse circuitry for counting failure events
Granted: April 15, 2025
Patent Number:
12276706
The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nth stage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nth stage may include an Nth fuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nth electronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector…
Field effect transistors with gate fins and method of making the same
Granted: April 15, 2025
Patent Number:
12279445
A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all…
Configurable capacitors with 3D non-volatile array
Granted: April 15, 2025
Patent Number:
12279430
A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.
Three-dimensional memory device with staircase etch stop structures and methods for forming the same
Granted: April 15, 2025
Patent Number:
12279425
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for…
Removable memory card with efficient card lock mechanism, XY ratios, and pads layout
Granted: April 15, 2025
Patent Number:
12277465
A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
Apparatus and methods for back-to-back state machine controller bus operations
Granted: April 15, 2025
Patent Number:
12277347
An apparatus is provided that includes a memory structure including non-volatile memory cells, a first processor and a second processor. The first processor is configured to provide a plurality of sets of commands to a second processor to perform memory operations on the non-volatile memory cells. The second processor is configured to execute the sets of commands and provide a control signal to the first processor. The first processor is further configured to provide the sets of commands…
Scatter gather list adaptive bucketing
Granted: April 15, 2025
Patent Number:
12277345
The present disclosure generally relates to memory management during SGL fetching. When a data storage device is required to fetch an SGL from a host device, the data storage device cannot determine how much memory will be required to be allocated. The disclosure herein reduces the impact of the problem of under or over allocating memory and over-fetching, thereby reducing performance of the device during transfers. The disclosure provides guidance on how to implement an adaptive…
Flash interface with switching logic
Granted: April 15, 2025
Patent Number:
12277344
There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the…
Selectable performance-based partitioning
Granted: April 15, 2025
Patent Number:
12277334
A data storage device includes storage media and control circuitry and is configured to enable the creation of partitions with different performance levels. The storage media includes a first set and a second set of memory blocks having different performance levels. The control circuitry is configured to: in response to a request from a host system, provide performance data from the first set of memory blocks and the second set of memory blocks to the host system. The control circuitry…
ATS PRI support with implicit cache
Granted: April 15, 2025
Patent Number:
12277061
The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated…
Semiconductor wafer configured for single touch-down testing
Granted: April 8, 2025
Patent Number:
12270853
A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
Semiconductor device including through-package debug features
Granted: April 8, 2025
Patent Number:
12272609
A method of forming a semiconductor device includes through-package debug features enabling debug of a BGA package while mounted to a printed circuit board or other host device. In one example, the through-package debug features are filled or plated vias extending from a surface of the semiconductor device, through a device housing, down to test pads on the substrate. In another example, the through-package debug features are open channels formed from a surface of the semiconductor…
Reverse garbage collection process for a storage device
Granted: April 8, 2025
Patent Number:
12271617
A memory device includes a number of different memory dies and/or planes. One or more host operations, such as write operations and/or read operations, are performed on each memory die and/or plane in sequence. For example, from memory die 0 to memory die n. A garbage collection process is performed in parallel with the host operations. However, the garbage collection process is performed in a reverse order when compared with the order of the host operations. For example, the garbage…
Peer storage device messaging for vulnerability management
Granted: April 8, 2025
Patent Number:
12271486
Systems and methods for peer data storage device messaging over a peer channel, such as a control bus, for vulnerability management are disclosed. Storage devices may include a host interface configured to connect to a host system and a peer interface to establish peer communication independent of host availability. The storage devices may determine security issues (for themselves or for peer storage devices) and send a threat notification through the peer interface, enabling peer…
Providing host with multiple mapping information that span across multiple HPB regions
Granted: April 8, 2025
Patent Number:
12271301
A storage device minimizes HPB entry inactivation resulting from data associated with hot reads being retrieved from multiple HPB sub-regions covering a logical-to-physical table. The storage device may support the HPB feature and a multiple HPB sub-region mode. The storage device includes a controller that tracks a hit count associated with a logical block address in a read command. The controller determines that the hit count has reached a hit threshold and updates a hit table to…
Data storage device and method for host-assisted improved error recovery using a correlation factor
Granted: April 8, 2025
Patent Number:
12271261
A data storage device and method for host-assisted improved error recovery using a correlation factor are provided. In one embodiment, the data storage device receives, from a host, an indication that data associated with a first logical address is correlated with data associated with a second logical address; determines a correlation factor based on a degree of correlation between the data associated with the first logical address and the data associated with the second logical address;…
Current reference circuit with process, voltage, and wide-range temperature compensation
Granted: April 8, 2025
Patent Number:
12271217
Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on…
