Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same
Granted: February 4, 2025
Patent Number:
12219776
A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an…
Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
Granted: February 4, 2025
Patent Number:
12219756
A memory device includes at least one instance of a unit layer stack including a source layer, a channel-containing layer that contains a semiconductor channel, and a drain layer that are stacked along a vertical direction over a substrate; a memory opening vertically extending through the at least one instance of the unit layer stack; and a memory opening fill structure located in the memory opening and including a control gate electrode and a memory film in contact with each instance…
Methods and apparatuses for forming semiconductor devices containing tungsten layers using a tungsten growth suppressant
Granted: February 4, 2025
Patent Number:
12217965
A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.
SSD auxiliary battery power for handling ungraceful shutdown with host
Granted: February 4, 2025
Patent Number:
12216920
Aspects of a storage device, a host device, and a redundant array of independent disks (RAID) system including multiple storage devices and the host device are provided that provide power control and power loss handling. The host device and the storage devices in the RAID system may each include at least a memory, a controller coupled to the memory, and a power management circuit coupled to the memory and the controller. A storage device controller may receive rationed power from the…
ZQ calibration circuit and method for memory interfaces
Granted: February 4, 2025
Patent Number:
12216596
Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process…
Three-dimensional memory device with finned support pillar structures and methods for forming the same
Granted: January 28, 2025
Patent Number:
12213320
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through a first region of the alternating stack, memory opening fill structures located in the memory openings, and support pillar structures vertically extending through a second region of the alternating stack. Each of the support pillar structures includes a central columnar structure and a set of fins…
Optical measurement tool containing chromatic aberration enhancement component and optical alignment method using the same
Granted: January 28, 2025
Patent Number:
12211724
An optical alignment method includes providing an emitted radiation beam which includes a first peak wavelength and a second peak wavelength to a chromatic aberration enhancement component which increases a chromatic aberration of the emitted radiation beam, providing a first incident radiation beam having the first peak wavelength and a second incident radiation beam having the second peak wavelength which is shorter than the first peak wavelength to respective first and second…
Magnetoresistive memory device and method of operating same using ferroelectric-controlled exchange coupling
Granted: January 28, 2025
Patent Number:
12211535
A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy…
Data storage device and method for dynamic logical page write ordering
Granted: January 28, 2025
Patent Number:
12210452
In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.
Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same
Granted: January 21, 2025
Patent Number:
12207459
A bonded assembly includes a backside peripheral circuit, a memory die and a first logic die. The memory die includes a doped semiconductor material layer, a three-dimensional memory array, and memory-side metal interconnect structures and first memory-side bonding pads embedded in memory-side dielectric material layers. The first logic die includes a logic-side peripheral circuit including a first subset of logic devices configured to control operation of the three-dimensional memory…
Unaligned deallocated logical blocks datapath support
Granted: January 21, 2025
Patent Number:
12204753
The present disclosure generally relates to improved unaligned deallocated logical block transfer. Rather than stalling the data-path in unaligned deallocated LBA scenarios, the data-path will work regularly while ignoring the unaligned deallocated indication. The old and non-valid data received for the unaligned deallocated LBA will be written to the host. The device controller will detect the unaligned deallocated LBA and overwrite the data with other values such as 0's or 1's as…
Test controller enabling a snapshot restore and resume operation within a device under test
Granted: January 21, 2025
Patent Number:
12205660
Techniques are provided for capturing a processing state snapshot of a device under test (DUT) that enable a previous test run to be restored and resumed from the same point the snapshot was taken. The techniques enable restoring the snapshot into the same or a different device to resume a previous test run. In an illustrative example, a DUT is controlled by a Joint Test Action Group (JTAG) test controller to capture a Steady State Snapshot by controlling peripheral components of the DUT…
Systems and methods for retaining inflight data during a power loss event
Granted: January 21, 2025
Patent Number:
12205658
Memory devices, or memory systems, described herein may include a controller (e.g., SSD controller) and a NAND memory device for storing inflight data. When the power loss event occurs, a memory system maintains (i.e., not un-select) the existing memory block being programmed at the time of power loss. The existing program operation at the event of power loss can be suspended by controller. The inflight data can be re-sent by controller directly to NAND latches, when power loss event was…
Hybrid smart verify for QLC/TLC die
Granted: January 21, 2025
Patent Number:
12205657
Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory…
MLC programming techniques in a memory device
Granted: January 21, 2025
Patent Number:
12205654
The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the…
Overwrite read methods for resistance switching memory devices
Granted: January 21, 2025
Patent Number:
12205640
A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.
Concurrent write to programmable resistance memory cells in cross-point array
Granted: January 21, 2025
Patent Number:
12205638
Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced…
Non-volatile memory die with bit-flip object insertion
Granted: January 21, 2025
Patent Number:
12205252
Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of…
Dropout in neutral networks using threshold switching selectors in non-volatile memories
Granted: January 21, 2025
Patent Number:
12205008
A non-volatile memory device is configured for in-memory computation of layers of a neural network by storing weight values as conductance values in memory cells formed of a series combination of a threshold switching selector, such as an ovonic threshold switch, and a programmable resistive element, such as a ReRAM element. By scaling the input voltages (representing inputs for the layer of the neural network) relative to the threshold values of the threshold switching selectors,…
SSD use of host memory buffer for improved performance
Granted: January 21, 2025
Patent Number:
12204756
Aspects of a storage device are provided that requests L2P address translation data from an HMB for execution of an associated host command using a dynamically determined HMB transfer size. The storage device includes a volatile memory and a controller. The controller allocates, in the volatile memory, multiple memory locations for L2P address translation data from an HMB. The controller receives a command indicating a host data length, and transmits a request for a portion of the L2P…
