Three-dimensional memory device with vertical field effect transistors and method of making thereof
Granted: April 16, 2024
Patent Number:
11963352
A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect…
Memory device that is optimized for operation at different temperatures
Granted: April 16, 2024
Patent Number:
11961573
A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line…
Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain side select gate technology
Granted: April 16, 2024
Patent Number:
11961572
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells…
Balancing peak power with programming speed in non-volatile memory
Granted: April 16, 2024
Patent Number:
11961563
Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc…
Memory cell group read with compensation for different programming speeds
Granted: April 9, 2024
Patent Number:
11955184
Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the…
Adaptive pre-programming
Granted: April 9, 2024
Patent Number:
11955182
Adaptive and dynamic control of the duration of a pre-program pulse based on a number of planes selected for the pre-program operation is disclosed. A value for a pre-program time increment parameter may be selected based on the number of planes for which the pre-program operation will be performed or determined based on a predefined association with the number of planes. A pre-program voltage pulse may then be applied for a duration that is equal to a default duration for a single-plane…
Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same
Granted: April 2, 2024
Patent Number:
11948902
A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die…
Implementation of deep neural networks for testing and quality control in the production of memory devices
Granted: April 2, 2024
Patent Number:
11947890
Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural…
Variable bit line bias for nonvolatile memory
Granted: March 26, 2024
Patent Number:
11942157
An apparatus is provided that includes a word line coupled to a word line driver circuit, bit lines, a plurality of non-volatile memory cells each coupled to the word line and a corresponding one of the bit lines, and a control circuit coupled to the word line and the bit lines. The control circuit is configured to program the memory cells by causing the word line driver to apply a program pulse to the word line, and biasing each bit line to a corresponding bit line voltage that has a…
Three-dimensional memory device and method of making thereof using double pitch word line formation
Granted: March 26, 2024
Patent Number:
11942429
A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are…
Three-dimensional memory device containing self-aligned bit line contacts and methods for forming the same
Granted: March 19, 2024
Patent Number:
11935784
A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity…
Free flow data path architectures
Granted: March 19, 2024
Patent Number:
11935622
A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by…
Burst programming of a NAND flash cell
Granted: March 19, 2024
Patent Number:
11935599
A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after…
Dummy cell resistance tuning in NAND strings
Granted: March 19, 2024
Patent Number:
11935593
An apparatus includes a control circuit configured to connect to memory cells connected in series in NAND strings. Each NAND string includes a plurality of data memory cells coupled to a plurality of data word lines in series with a plurality of dummy memory cells connected to a plurality of dummy word lines. The control circuit configured to apply a first dummy word line voltage to one or more dummy word lines of the plurality of dummy word lines in a verify step of a program operation…
Pseudo multi-plane read methods and apparatus for non-volatile memory devices
Granted: March 19, 2024
Patent Number:
11935585
An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured…
Window program verify to reduce data latch usage in memory device
Granted: March 12, 2024
Patent Number:
11929125
Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds,…
Determining charge pump efficiency using clock edge counting
Granted: March 12, 2024
Patent Number:
11927635
A charge pump test configuration and corresponding method of operation are disclosed for determining charge pump efficiency without needing to obtain direct current measurements. A first number of clock edges (CEs) of a clock signal supplied to a first charge pump is determined over a period of time for a predetermined output current. The first charge pump is then connected with a charge pump under test (PUT) in a cascaded manner such that an output current of the first charge pump is…
Data retention reliability
Granted: March 5, 2024
Patent Number:
11923019
The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the…
Three-dimensional memory device including sense amplifiers having a common width and separation
Granted: March 5, 2024
Patent Number:
11925027
A semiconductor structure includes a memory array including first and second bit lines and a sense amplifier circuit. The sense amplifier circuit includes a first sense amplifier array containing first active sense amplifier transistors that each have an active region having a first width, where the first active sense amplifier transistors are electrically connected to the first bit lines, and a second sense amplifier array including second active sense amplifier transistors that each…
Three-dimensional memory device including dielectric rails for warpage reduction and method of making the same
Granted: March 5, 2024
Patent Number:
11923321
A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal…
