Method for modeling and updating a colorimetric reference profile for a flat panel display
Granted: May 6, 2003
Patent Number:
6559826
A method and system for updating the colorimetric characteristics of a flat panel display over the display's entire lifetime. An advantage of the present invention is that the useful life and the color accuracy of a flat panel display can be extended. In one embodiment of the invention, an initial set of luminance data of a flat panel monitor is programmed into addressable memory locations within that monitor. Thereafter, the luminance output of the lamps of the flat panel monitor…
High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
Granted: April 29, 2003
Patent Number:
6556197
A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a…
Set of multi-device faceplates
Granted: April 22, 2003
Patent Number:
D473561
Parameterization of subdivision surfaces
Granted: April 22, 2003
Patent Number:
6553337
A method for parameterizing a subdivision mesh in a computer system, the subdivision mesh comprising at least two faces, at least two faces sharing an edge, includes assigning a unique index for each of the at least two faces, assigning, for each of the at least two faces, a first (u) and a second (v) parameter to uniquely parameterize each point on a respective face, each respective u and v parameters for a respective face also being assigned the unique index for that respective face;…
Modular input/output controller capable of routing packets over busses operating at different speeds
Granted: April 22, 2003
Patent Number:
6553446
A modular, scalable high-bandwidth computer architecture. A single integrated router/bridge ASIC defines a family of peripheral controllers that accept high-speed packet switched data, either for routing to other, identical controllers, or for routing to on-board PCI buses, or a combination of the two destinations, depending on the number of ASICs employed and their selectable configuration.
System for user customization of attributes associated with a three-dimensional surface
Granted: April 15, 2003
Patent Number:
6549212
The present invention is a system that allows a user to paint surface related attributes just like texture is painted. The painting actions are in the form of scripts that the user can provide and which are interpreted during painting.
Method and system for determining repeater allocation regions
Granted: April 15, 2003
Patent Number:
6550048
A system and method for determining a repeater allocation region is disclosed. A path delay equation describing a path delay from a driver to a gate is formulated. A delay constraint is applied to the path delay equation. A repeater allocation region indicating a position of a repeater is determined from the path delay equation.
Method and system for efficient edge blending in high fidelity multichannel computer graphics displays
Granted: April 8, 2003
Patent Number:
6545685
A method for implementing edge blending between a first and second video frame to create a seamless multichannel display system. The method is implemented in a graphics computer system including a processor coupled to a memory via a bus. Within the computer system, a first video frame is rendered for display on a first video channel. A second video frame is rendered for display on a second channel. A first overlap region is rendered onto the first frame to obtain a first blended video…
Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
Granted: April 8, 2003
Patent Number:
6546451
A node controller (12) includes a processor interface unit (24), a crossbar unit (26), and a memory directory interface unit (22). Request and reply messages pass from the processor interface unit (24) to the crossbar unit (26) through a processor interface output queue (52). The processor interface unit (24) writes a request message into the processor interface output queue (52) using a processor interface clock to latch a write address from a write address latch (62) in a synchronizer…
Electrically conductive path through a dielectric material
Granted: April 1, 2003
Patent Number:
6541853
A structure and method thereof for providing an electrically conductive path between a first conductive point and a second conductive point. The structure includes an insulating material disposed between the first conductive point and the second conductive point. A dipole material is distributed within the insulating material. The dipole material is comprised of randomly oriented magnetic particles. The magnetic particles in a selected localized region of the insulating material are…
Multiple light source color balancing system within a liquid crystal flat panel display
Granted: March 18, 2003
Patent Number:
6535190
A system for color balancing within a liquid crystal flat panel display unit. The present invention includes a method and system for altering the brightness of two or more light sources, having differing color temperatures, thereby providing color balancing of a liquid crystal display (LCD) unit within a given color temperature range. The embodiments operate for both edge and backlighting systems. In an embodiment, two planar light pipes are positioned, a first over a second, with an air…
System and method for distributing output queue space
Granted: March 11, 2003
Patent Number:
6532501
A system and method for distributing output queue space is provided that includes an output queue (18), a input queue (12), an asynchronous input queue (14), and a credit allocation module (22). The output queue (18) has a certain number of output spaces (19) where each output space (19) represents an output queue credit. The output queue (18) releases output queue credits when releasing data from output spaces (19) and receives data in response to a command being processed from the…
Method and system for calculating interconnect moments and delay
Granted: March 11, 2003
Patent Number:
6532575
A system and method for calculating interconnect response and delay are disclosed. The admittance of the nodes of an interconnect is determined from the attributes of the nodes. Weighted admittance of the nodes are determined from the admittance, and transfer function coefficients are determined the weighted admittance. A transfer function is determined from the transfer function coefficients, and is used to calculate an interconnect delay.
Data synchronizer for a multiple rate clock source and method thereof
Granted: March 4, 2003
Patent Number:
6529570
A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a…
Floating-point adder performing floating-point and integer operations
Granted: March 4, 2003
Patent Number:
6529928
An apparatus and a method are disclosed for performing both floating-point operations and integer operations utilizing a single functional unit. The floating-point adder performs logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of…
System for attaching rigid objects to deformed shapes in computer generated images via real time local approximation of deformation using rotation
Granted: February 25, 2003
Patent Number:
6525735
The present invention is a system that produces a position of a rigid object, such as a button, on a deformed model, such as an animated piece of cloth, at each cycle in an animation of the model by isotropically finding a linear approximation of the deformation at the model and finding a rotation of the object allowing attachment of the object to the model. The system removes shear and scaling from a linear transformation of an average deformation of the model. A volumetric area of the…
Discrete delay line system and method
Granted: February 11, 2003
Patent Number:
6518812
A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the…
Electronic device support and method
Granted: February 4, 2003
Patent Number:
6513770
An improved support bracket for supporting electronic devices provides improved adjustability and alignment. The support bracket includes a front surface and a rear surface each including a portion having at least one threaded hole and a support portion between the front surface and rear surface for supporting an electronic device. The support bracket includes a side portion having a mechanism for coupling the side portion to a structure, a guide portion and a support portion for…
Partitioning a distributed shared memory multiprocessor computer to facilitate selective hardware maintenance
Granted: February 4, 2003
Patent Number:
6516372
A distributed shared memory multiprocessor computer system is provided, which has a number of processors and is divided into partitions. Each partition has within it one or more of the processors, and may also have memory or cache and other related hardware. Although each partition works together and communicates with other partitions to share computational load, the partitions each are independently operable and execute an independent copy of the operating system. The partitions…
Printed circuit board stiffener
Granted: January 28, 2003
Patent Number:
6512676
Apparatus and methods for reducing circuit board flexing is presented. The apparatus is fastened to a printed circuit board to provide rigid support for reducing bending and flexing. In one embodiment, a rigid frame is provided that is adapted to be fastened to one or more components and to be fastened to a printed circuit board. The frame is adapted to elevate the attached component from the PCB surface allowing components to be mounted on the PCB therewith. The frame is adapted to…
