Method and apparatus for producing, controlling and displaying menus
Granted: September 9, 2003
Patent Number:
6618063
A system that combines a radial marking menu portion with a linear menu portion in a single menu display. Item selection in the linear portion is performed by location selection using a pointing device. Item selection in the marker portion is determined by the pattern of a stroke made by the pointing device with the system ignoring linear menu items across which the stroke completely passes.
Method and apparatus for preparing a perspective view of an approximately spherical surface portion
Granted: September 9, 2003
Patent Number:
6618049
A computer system (10) can prepare and present on a display (22) a two-dimensional image that includes a perspective view, from a selected eyepoint (71, 152), of an object (23) which is a three-dimensional object of an approximately spherical shape, such as the earth. The system maintains image information for the object at each of several different resolution levels, portions of which are selected and mapped into the perspective view for respective portions of the surface of the object.…
Method and system for hybrid mapping of objects into a relational data base to provide high-speed performance and update flexibility
Granted: September 2, 2003
Patent Number:
6615204
A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is…
System and method for providing a wide aspect ratio flat panel display monitor independent white-balance adjustment and gamma correction capabilities
Granted: August 26, 2003
Patent Number:
6611249
A system and method are described herein for controlling the white balance and providing gamma correction without compromising gray-scale dynamic range in a flat panel liquid crystal display (LCD). According to one embodiment of the present invention, the flat panel LCD includes electronic circuitry for coupling to a host computer to receive a white-balance adjustment control signal, and electronic circuitry for receiving image data to be rendered on the flat panel LCD. Further, the flat…
Translation of PCI level interrupts into packet based messages for edge event drive microprocessors
Granted: August 5, 2003
Patent Number:
6604161
Translation of PCI level interrupts into packet based messages for edge event drive microprocessors includes, a bridge device receiving interrupts via an interrupt line from one or more PCI devices. The bridge device further sends an interrupt write packet to a CPU to launch the interrupt routine. The interrupt routine services the interrupt and the PCI device negates the interrupt line. At this point, the CPU generates a non-blocking write. This write causes the bridge to check the…
Distribution of address-translation-purge requests to multiple processors
Granted: August 5, 2003
Patent Number:
6604185
A method and apparatus for deallocating memory in a multi-processor, shared memory system. In one aspect, a node in the system has a node controller that contains sequencing logic. The sequencing logic receives a command across a network. The sequencing logic translates the received command into a Purge Translation Cache (PTC) instruction and sends the PTC instruction across a bus to a processor. The processor contains bus control logic that receives the PTC instruction and purges a…
Method and apparatus for representing, manipulating and rendering solid shapes using volumetric primitives
Granted: July 29, 2003
Patent Number:
6600487
A method and apparatus for modeling three-dimensional solid objects are provided. The method of the present invention uses the concept of volumetric objects. Each volumetric object is a decoupled combination of volumetric geometry and volumetric appearance. To be rendered, one or more volumetric objects are tessellated into a series of one or more volumetric primitives. The volumetric primitives are then polygonized. The result is a list of two-dimensional polygons. The list of polygons…
System, method and computer program product for implementing scalable multi-reader/single-writer locks
Granted: July 29, 2003
Patent Number:
6601120
An scalable multi-reader/single-writer lock implementation that eliminates contention for lock data structures that can occur in large symmetric multi-processing (SMP) computer systems. The present invention includes a registry head data structure for each critical resource within the computer system. Linked to each of the registry head data structures are one or more client data structures that represent each client (i.e., process, thread, interrupt handler, and the like) that needs…
Diagnostic system and method for a highly scalable computing system
Granted: July 29, 2003
Patent Number:
6601183
Diagnostic environments designed for ccNUMA computing systems require different capabilities than conventional diagnostic programs. Since most conventional operating systems do not permit sufficient access to hardware by application programs, a diagnostic microkernal is distributed to all of the processors of all of the nodes of the computing system. Instead of dumping output to a user interface, diagnostic programs executing under control of the diagnostic microkernal store formatted…
Input/output device managed timer process
Granted: July 15, 2003
Patent Number:
6594787
A system and method thereof for monitoring elapsed time for a transaction. A computer system executes an application to initiate a transaction. An input/output device communicatively coupled to the computer system receives the transaction from the computer system. The input/output device is adapted to have a timer for measuring time until, for example, a response to the transaction is generated. The input/output device monitors the timer to identify when a time period allotted for the…
High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
Granted: July 15, 2003
Patent Number:
6593929
A low cost high performance three dimensional (3D) graphics system is disclosed that can model a world in three dimensions and project the model onto a two dimensional viewing plane selected based on a changeable viewpoint. The viewpoint can be changed on an interactive, real time basis by operating user input controls such as game controllers. The system rapidly produces a corresponding changing image (which can include animated cartoon characters or other animation) on the screen of a…
Method and computer program product for subdivision generalizing uniform B-spline surfaces of arbitrary degree
Granted: July 1, 2003
Patent Number:
6587105
A method and computer program product are presented for converting an arbitrary mesh to a subdivision surface. Where the subdivision surface is to have an odd degree d=2m+1 on the regular part of the mesh, the method includes the steps of subdividing the mesh in a linear fashion, then iteratively smoothing the subdivided mesh m times. Where the subdivision surface is to have an even degree d=2m on the regular part of the mesh, the method includes the steps of…
Method and apparatus for handling invalidation requests to processors not present in a computer system
Granted: June 10, 2003
Patent Number:
6578115
A node controller (12) in a computer system (10) includes a processor interface unit (24), a memory directory interface unit (22), and a local block unit (28). In response to a memory location in a memory (17) associated with the memory directory interface unit (22) being altered, the processor interface unit (24) generates an invalidation request for transfer to the memory directory interface unit (22). The memory directory interface unit (22) provides the invalidation request and…
System and method for high-speed execution of graphics application programs including shading language instructions
Granted: June 10, 2003
Patent Number:
6578197
A system and method for high-speed execution of graphics application programs, including shading language instructions, that utilize 3D graphics hardware. The method involves expressing a graphics computation in a platform-independent procedural shading expression, converting the expression (i.e., user application program) into an intermediate representation such as a tree, and then translating it into a sequence of parametric shading expressions. The method can alternatively processes…
System for communications where first priority data transfer is not disturbed by second priority data transfer and where allocated bandwidth is removed when process terminates abnormally
Granted: June 3, 2003
Patent Number:
RE38134
The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer…
Housing ground bracket and method
Granted: June 3, 2003
Patent Number:
6574121
A ground bracket and method for grounding an electronic device to a structure such as a rail, rack or cabinet. According to one aspect of the invention the ground bracket has a first conductive surface for use in coupling the bracket to the structure and an arcuate portion conductively coupled to the first conductive surface for contacting an electronic device. In another embodiment, a bracket includes a first surface for coupling to a rack, and a portion positioned proximal a computer…
Method and computer program product for global minimization of sign-extension and zero-extension operations
Granted: May 27, 2003
Patent Number:
6571387
A method and computer program product, within an optimizing compiler, for the global minimization of sign-extension and zero-extension operations in generated code during compilation. The method and computer program product allows, for example, 64-bit compilers targeting the Intel IA64 architecture to improve their SPECint benchmarks by reducing the number of sign-extension and zero-extension operations in the global and intra-procedural scope, thus, speeding up the execution of the…
Preemptive timer multiplexed shared memory access
Granted: May 20, 2003
Patent Number:
6567426
The present invention is directed to a method and system for sharing a data memory among a plurality of processors in a computer system. In the system and method of the present invention, a plurality of processors are coupled to a data memory for accessing the data memory in N-bit bandwidth. The present invention receives an active signal for accessing the data memory from the plurality of processors. A processor requesting accessing to the data memory asserts an active signal. Among the…
Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code
Granted: May 20, 2003
Patent Number:
6567976
A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of “unroll and jam” on selected loop nests. The present invention allows any arbitrarily deep loop nests with non-varying loop bounds to be properly unrolled even in the presence of imperfectly nested code. This is accomplished for two-deep loop nests by transforming the code into multiple adjacent loop nests. In the transformed code, the…
Method and system for handling interrupts in a node controller without attached processors
Granted: May 13, 2003
Patent Number:
6564277
A node controller (12) includes a processor interface unit (24) that receives an interrupt signal (50). The processor interface unit (24) includes a register (52) with a forward enable bit (54). In response to the forward enable bit (54) being set, the processor interface unit (24) generates a forward interrupt signal (56) for transfer to an input/output interface unit (26) of the node controller (12). The input/output interface unit (26) generates an interrupt request for transfer to a…
