Method and apparatus for antialiasing raster scanned images
Granted: December 3, 1996
Patent Number:
5581680
A method and apparatus for drawing at least a two pixel wide antialiased line is described in which the apparatus utilizes an interpolator, having a set up unit and an iterator unit, and a blender. The set up unit determines various parameters of the line to be drawn and selects a pair of pixels adjacent to and straddling an idealized line representing the line to be drawn. The iterator unit determines the coverages of the pair of pixels based on the parameters output by the set up unit.…
TLB with two physical pages per virtual tag
Granted: November 12, 1996
Patent Number:
5574877
A TLB which has at least two page frame numbers (PFN) associated with each tag (Virtual Page Number) is provided. Thus, a match will produce two possible physical page frame numbers. The selection between these two is controlled by a bit provided directly from the virtual address, without translation. This bit is preferably the least significant bit of the virtual page number, or the first bit after the physical offset. This structure effectively doubles the capacity of the TLB without…
System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes
Granted: November 5, 1996
Patent Number:
5572704
A method for preventing data loss and deadlock in a multi-processor computer system wherein at least one processor in the computer system includes a split-level cache. The split-level cache has a byte-writable first-level and a word-writable second level. The method monitors the second level cache to determine if a forced atomic (FA) instruction is in a second level cache pipeline. If an FA instruction is determined to be in the second level cache pipeline, then interventions to the…
System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders
Granted: November 5, 1996
Patent Number:
5572713
A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that…
RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory
Granted: October 22, 1996
Patent Number:
5568442
A RISC processor utilizes a segmented cache to reduce word line loading to reduce power consumption and increase speed. Address bit are predecoded to activate a selected segment. Groups of instructions are accessed from the cache in parallel and stored in register. The stored instructions are fetched from the register during sequential instruction execution to reduce the number of cache accesses.
Backward-compatible computer architecture with extended word size and address space
Granted: October 22, 1996
Patent Number:
5568630
A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended…
Disk drive bracket
Granted: October 15, 1996
Patent Number:
5564804
A bracket for securing a computer drive within a housing. The housing has a housing base, and two housing walls each disposed perpendicularly to the housing base and to each other. The bracket comprises a base for supporting the computer drive. The base has a first base aperture for slidably securing the bracket within the housing and for preventing movement of the bracket in a first degree of freedom. The bracket also comprises a first support means, which is perpendicularly coupled to…
Computer mouse
Granted: September 17, 1996
Patent Number:
D373760
System and method of generating object code using aggregate instruction movement
Granted: September 17, 1996
Patent Number:
5557761
A system and method of generating object code from an intermediate representation of source code is described. The intermediate representation includes a plurality of basic blocks each being represented by a plurality dam dependency graphs, wherein each data dependency graph comprises a plurality of nodes each corresponding to an instruction from the target computer instruction set. The present invention operates by selecting a source basic block (that is one of the basic blocks of the…
Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
Granted: September 10, 1996
Patent Number:
5555384
Methods and apparatus for optimizing the operation of an instruction pipeline in a computer are disclosed. The methods and apparatus function at both the effective beginning and end of the pipeline. At the pipeline's beginning, a Pipeline Controller monitors the availability of data for various floating point operations. Data is read at either a fast or slow rate, depending on its availability, and instructions are allowed to proceed through the pipeline based on this data availability.…
Method and apparatus for navigation within three-dimensional information landscape
Granted: September 10, 1996
Patent Number:
5555354
A method and apparatus for navigating within a three dimensional graphic display space and manipulating information and data represented by objects in display space. The method and apparatus presents users with a vastly expanded view of their data, displayed with a richer dimensionality. Data objects represented by graphic objects are arranged into a navigable landscape representing the containership and contextual relations of the underlying data. The graphic objects are columns,…
Apparatus and method for integrating texture memory and interpolation logic in a computer system
Granted: August 20, 1996
Patent Number:
5548709
In a computer graphics system, a semiconductor chip used in performing texture mapping. Textures are input to the semiconductor chip. These textures are stored in a main memory. Cache memory is used to accelerate the reading and writing of texels. A memory controller controls the data transfers between the main memory and the cache memory. Also included within the same semiconductor chip is an interpolator. The interpolator produces an output texel by interpolating from textures stored…
System and method for generating a read-modify-write operation
Granted: August 6, 1996
Patent Number:
5544331
A computer based system and method for implementing a read-modify-write operation in a computer based system comprising a first bus and a second bus, wherein the second bus is not transaction based. The method includes the steps of determining whether a first device connected to the first bus has issued on the first bus a read transaction comprising a predetermined trigger address, acquiring the second bus in accordance with the determination, reading data via the second bus from a…
Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache
Granted: July 30, 1996
Patent Number:
5542062
A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses…
Debug mode for a superscalar RISC processor
Granted: July 16, 1996
Patent Number:
5537538
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point…
Method and apparatus for displaying data within a three-dimensional information landscape
Granted: June 18, 1996
Patent Number:
5528735
A method and apparatus are presented for displaying three-dimensional navigable display space containing an aggregation of graphical objects and an overview of the aggregation of display objects. An altered perspective is provided by compressing the horizontal dimension of the displayed objects so that a user can see a representative overview of the entire aggregation of display objects that have been selected for display together on a display screen. The compressed component is expanded…
Processor-based method for rasterizing polygons at an arbitrary precision
Granted: June 18, 1996
Patent Number:
5528737
An image processor is provided which rasterizes polygons with a minimum of computation. Pixels are tested for being inside a triangle by sorting the vertices by their values in one coordinate, rounding the vertices to the nearest pixels, and calculating two characteristic functions for pixels one scan line at a time, thereby identifying two end pixels for the scan line, where the particular functions used are edge characteristic functions for the two edges which bound pixels in the scan…
Method and apparatus for antialiasing raster scanned, polygonal shaped images
Granted: June 18, 1996
Patent Number:
5528738
A method and apparatus for drawing at least a one pixel wide antialiased line on an edge of a filled polygon. The apparatus comprises an interpolator, having a set up unit and an iterator unit, and a blender. The set up unit determines various parameters of the line to be drawn and selects a pair of pixels adjacent to and straddling an idealized line representing the line to be drawn, where the first pixel is claimed by the edge of the polygon as a filled pixel. The iterator unit…
Three dimensional model with three dimensional pointers and multimedia functions linked to the pointers
Granted: June 11, 1996
Patent Number:
5526478
A computer implemented method of annotating a geometric figure displayed and manipulable in three-dimensional representation on a display of a computer system with a pointer is described. The pointer is also displayed and manipulable in three-dimensional representation on the display. The method associates multimedia functions with the geometric figure. The pointer is positioned to point at an area of the geometric figure using a control device. The geometric figure is displayed in a…
Variable page size translation lookaside buffer
Granted: June 11, 1996
Patent Number:
5526504
A set associative translation lookaside buffer (TLB) that supports variable sized pages without requiring the use of a separate block TLB. The TLB includes a hashing circuit that creates an index into the TLB for a virtual address using different bits from the virtual address depending on the page size of the address, and a comparator that compares virtual address identifiers or portions of virtual address identifiers stored in the TLB to the current virtual address to determine if a…
