Central processing unit for processing a plurality of threads using dedicated general purpose registers and masque register for providing access to the registers
Granted: June 4, 1996
Patent Number:
5524250
A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the…
System for booting computer for operation in either one of two byte-order modes
Granted: June 4, 1996
Patent Number:
5524245
A system for abstracting the byte ordering of a computer firmware from the operating system by allowing a computer to automatically change endianness under full software control. The byte ordering can be switched completely transparent to the end user during system boot. The system is comprised of hardware and software to run either byte order stand alone software or operating systems on demand.
Method and apparatus for rendering volumetric images
Granted: May 7, 1996
Patent Number:
5515484
A method for rendering a three dimensional graphic object in a two dimensional display space by segmenting the object into parallelepipeds and decomposing the parallelepipeds into rods of voxels that are parallel to the depth axis (Z) of the display and by projecting the rods of voxels onto the X-Y plane of the display as lines of pixels and a method for drawing antialiased volumetric images. An apparatus for implementing both methods includes an interpolator, having a set-up unit and an…
Memory system including local and global caches for storing floating point and integer data
Granted: April 23, 1996
Patent Number:
5510934
A split level cache memory system for a data processor includes a single chip integer unit, an army processor such as a floating point unit, an external main memory and a split level cache. The split level cache includes an on-chip, fast local cache with low latency for use by the integer unit for loads and stores of integer and address data and an off-chip, pipelined global cache for storing arrays of data such as floating point data for use by the array processor and integer and…
System and method for fair arbitration on a multi-domain multiprocessor bus
Granted: April 16, 1996
Patent Number:
5509125
A multi-domain, distributed arbitration system, and a method performed by a plurality of arbiters to control arbitration of requests for a multiprocessor system bus. The requests are generated by a plurality of nodes coupled to the multiprocessor system bus. The requests are presented on a plurality of arbitration request lines. Each node comprises one of the arbiters such that each arbiter is associated with a corresponding node. A plurality of domains are created by the arbiters based…
Rotating sample of video images
Granted: April 9, 1996
Patent Number:
5506624
A computer-implemented method of transmitting images from a transmitter to a receiver (e.g. in a teleconferencing application). A receiver maintains an image in a local storage (e.g. that from a previous frame in a sequence of frames) and the transmitter receives an updated image for a next temporal period (e.g. the next frame). The transmitter divides the updated image into blocks and comparing a rotating pixel sample(s) of each of the blocks from the updated image with a sampled pixel…
Compact dual function adder
Granted: April 2, 1996
Patent Number:
5504698
A compact dual function adder circuit for providing both an addition operation for adding an input m-bit word to an input n-bit word, wherein m<n, and an increment operation for incrementing the input n-bit word, the dual function adder comprising a n-bit incrementer circuit, wherein the n-bit incrementer includes a first m-bit incrementer and a second n-m)-bit incrementer to provide a n-bit incrementer output sum. The n-bit incrementer output sum comprises an m-bit incrementer output…
System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
Granted: April 2, 1996
Patent Number:
5504874
A multiprocessing system that uses read resources to track cache coherent split transactions on its main system bus. Pending reads are tracked by being associated with read resources. When a read request is issued, it occupies the first available read resource. A pending read request will occupy a read resource until a corresponding read response appears on the bus. If all read resources are filled, future read requestors must wail until a read resource becomes available.
Method for clocking functional units in one cycle by using a single clock for routing clock inputs to initiate receive operations prior to transmit operations
Granted: February 27, 1996
Patent Number:
5495596
A method and circuit providing for an accurate sampling of data on a high speed bus in a computer system. Utilizing a single clock source, functional units that are capable of supporting two clock input sources, and a routing technique that provides for a receiving unit to be clocked prior to a transmitting unit, data transfer can occur reliably and economically on a high speed bus. Synchronization within a particular unit is accomplished by providing serial edge-triggered registers that…
Mechanism and method for integer divide involving pre-alignment of the divisor relative to the dividend
Granted: February 20, 1996
Patent Number:
5493523
A mechanism for dividing an integer dividend by an integer divisor to generate an integer quotient operates by aligning the divisor relative to the dividend such that a right-most bit of the divisor is aligned with a bit M of the dividend. The divisor is compared to an integer value whose right-most bits are equal to bits of the dividend which are aligned with bits of the divisor. As a result of this comparison, quotient bits which positionally correspond to the dividend bit M and to…
Top front and side portions of a combined computer housing and support stands
Granted: February 20, 1996
Patent Number:
D367269
Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25- or 64-bit data word
Granted: February 13, 1996
Patent Number:
5491702
An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1"s or by syndromes that contain exactly five "1"s in which bits 0-3 or 4-7 of the syndrome are all "1." Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1." All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that…
Loop scheduler
Granted: February 13, 1996
Patent Number:
5491823
A loop scheduler in a software compiler system for generating a schedule for executing in a target computer loops of instructions contained in a computer program is described. The loop scheduler operates by searching for an optimal loop schedule for executing a particular instruction loop in the target computer. The loop scheduler then identifies loop overhead instructions and non-loop overhead instructions in the particular instruction loop. A replicated loop schedule is generated by…
System and method of generating interactive computer graphic images incorporating three dimensional textures
Granted: February 6, 1996
Patent Number:
5490240
A system and method of interactively generating computer graphic images for incorporating three dimensional textures. The method of the present invention includes defining an orientation of a polygon relative to a plurality of three dimensional (3D) texture data sets, determining a level of detail of a pixel associated with the polygon, and selecting a first 3D texture data set and a second 3D texture data set from the plurality of 3D texture data sets in accordance with the pixel level…
Video camera used with personal computer
Granted: December 26, 1995
Patent Number:
D365585
Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same
Granted: December 26, 1995
Patent Number:
5479630
A cache memory system includes a primary cache characterized by a virtual index and physical tags, and a secondary cache characterized by a physical index and physical tag. Thus, the cache system forms a hybrid of physical-cache and virtual-cache characteristics. Further, the secondary cache includes a primary index segment for each line of secondary cache. The primary index segment corresponds to a portion of the virtual address for the contents stored at the respective secondary-cache…
System and method for adding detail to texture imagery in computer generated interactive graphics
Granted: November 28, 1995
Patent Number:
5471572
An apparatus and method for interactively magnifying a base texture to generate a generally unblurred magnified image of the base texture is disclosed. The present invention includes a base texture generator for filtering a high resolution source image to generate a base texture. A detail texture generator extracts a representative portion of high frequency information from the source image to generate a detail texture, wherein the detail texture comprises the extracted representative…
Bracket for a CPU daughter card
Granted: November 14, 1995
Patent Number:
5465934
A bracket for securing a daughter card within a computer housing. The computer housing having a housing base. The bracket having a bracket base. The bracket base having a base tab for slidably securing the bracket to the housing base. The bracket also has a securing means for engaging the daughter card and for securing the daughter card. The securing means has a first slot for accepting the daughter card and a second slot, perpendicularly aligned at a first end of the first slot, for…
Top, sides and front portions of a computer housing
Granted: October 31, 1995
Patent Number:
D363703
System for accessing graphic data in a SIMD processing environment
Granted: October 10, 1995
Patent Number:
5457779
An electronic logic and computer implemented apparatus and method for accessing graphic geometric data within a computer display system utilizing an SIMD environment. The present invention spreads the vertex data structure of geometric primitives across multiple memories allowing much higher bandwidth access into the data structure for greater performance. The present invention eliminates branches from the processing of triangle and quadrilateral primitives allowing full utilization of…
